EP610PC-25 vs EP610DC-25 Comparison
Detailed side-by-side comparison of EP610PC-25 by Altera and EP610DC-25 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DC-25
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 β ActiveSpecification Comparison
| Parameter | EP610PC-25 | EP610DC-25 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $9.95 |
| Device Family | Classic EPLD (EP610 series) | β |
| Macro Cells | 16 | β |
| Usable Gates | 300 | β |
| Propagation Delay (tpd) | 25 ns | β |
| Maximum Pipelined Data Rate | 100 MHz | β |
| Supply Voltage (Vcc) | 5 V (nominal) | β |
| Technology | CMOS, EPROM (UV-erasable) | CMOS EPROM (UV-erasable) |
| Device Type | OT PLD, PAL-type, CMOS | β |
| Dedicated Inputs | 4 | β |
| I/O Pins | 20 (bidirectional, JTAG-programmable OE per macrocell) | β |
| Package | PDIP-24 (0.3 inch, through-hole) | 24-pin CDIP (Ceramic DIP, through-hole) |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | 0 C to +70 C |
| Programming Method | EPROM (UV-erasable), via Altera programming hardware | JEDEC fuse-map / UV-erase |
| Mounting Type | Through-Hole (DIP) | Through Hole |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Family | β | Altera Classic EPLD |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Macrocells | β | 16 |
| Equivalent Gates | β | 300 |
| Maximum Propagation Delay (tPD) | β | 25 ns |
| Pipelined Data Rate | β | Up to 100 MHz |
| Number of I/O Pins | β | 22 |
| Number of Dedicated Inputs | β | 4 |
| Total Pin Count | β | 24 |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V (5 V nominal) |
| Speed Grade Suffix | β | -25 (25 ns tPD) |