EP610PC-25 - 16-Macrocell Classic EPLD, 25ns PDIP-24 | Altera
MPN: EP610PC-25 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
EP610PC-25 Overview
What is a Classic EPLD? An EPLD (Erasable Programmable Logic Device) is a type of Programmable Logic Device (PLD) that combines the non-volatility and simple programming model of a PAL (Programmable Array Logic) with the higher macrocell density of early complex PLDs. Classic EPLDs sit in the hierarchy between simple PAL/GAL devices and modern CPLDs/FPGAs, providing AND/OR plane logic with user-configurable macrocell flip-flops. EP610-class devices were commonly used to replace discrete 74LS glue logic and SSI/MSI PALs in 5 V industrial and computer-peripheral designs.
Key features include 16 macrocells (organized as four 16x8 PAL-like blocks of four macrocells each, with a sum term shared across each block), 24 dedicated input pins, 10 I/O pins, 33 product terms per macrocell, asynchronous clocking per macrocell, and architectural support for D, T, JK, and SR flip-flops. The EP610 is electrically erasable, allowing in-system reprogramming via the Altera programming algorithm.
The EP610PC-25 is built on a 5 V CMOS process with UV-erasable EPROM cells (the PC suffix denotes PDIP package). It supports synchronous or asynchronous register loading, programmable output enable per macrocell, and output macrocell polarity control. With 25 ns propagation delay and a 100 MHz internal pipelined data rate, it is positioned for glue-logic and interface-controller applications rather than high-density state machines.
Typical applications include 5 V glue-logic replacement in microprocessor systems, address decoding for 80-series CPUs, peripheral-interface controllers (bus arbitration, interrupt controllers, custom state machines), and legacy industrial-control retrofits. The PDIP-24 footprint is socket-friendly for prototype and through-hole assembly.
When designing with the EP610PC-25, allocate enough macrocell feedback for buried combinatorial logic; the AND-OR array is shared across each 16x8 block, so heavily skewed product-term distribution can limit fitting. Programming requires an Altera-compatible programmer (e.g., Altera Logic Programmer) and the MAX+PLUS II or AHDL+ toolchain.
This page synthesizes distributor pricing, legacy EPLD family equivalents, and application guidance not consolidated in the original Altera datasheet.
Drop-in alternatives for EP610PC-25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610PC-25 (same form factor and footprint) — differing in Package, Supply Voltage (VCC), Propagation Delay (tPD), Technology, Programming Method.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610PC-20
✅ Drop-In✓ In Stock
$47.8 / Unit
View Datasheet →EP610PC-15
✅ Drop-In✓ In Stock
$17.5 / Unit
View Datasheet →EP610PC-25T
✅ Drop-In✓ In Stock
$28.95 / Unit
View Datasheet →EP610LI-25
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$17.25 / Unit
View Datasheet →EP610DC-25
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$9.95 / Unit
View Datasheet →EP610PC-25 Maximum Ratings & Electrical Characteristics
| Device Family | Classic EPLD (EP610 series) |
| Macro Cells | 16 |
| Usable Gates | 300 |
| Propagation Delay (tpd) | 25 ns |
| Maximum Pipelined Data Rate | 100 MHz |
| Supply Voltage (Vcc) | 5 V (nominal) |
| Technology | CMOS, EPROM (UV-erasable) |
| Device Type | OT PLD, PAL-type, CMOS |
| Dedicated Inputs | 4 |
| I/O Pins | 20 (bidirectional, JTAG-programmable OE per macrocell) |
| Package | PDIP-24 (0.3 inch, through-hole) |
| Programming Method | EPROM (UV-erasable), via Altera programming hardware |
| Mounting Type | Through-Hole (DIP) |
EP610PC-25 Pin Configuration
| Pin 1 | I/O — Bidirectional I/O (macrocell) |
| Pin 2 | I/O — Bidirectional I/O (macrocell) |
| Pin 3 | I/O — Bidirectional I/O (macrocell) |
| Pin 4 | I/O — Bidirectional I/O (macrocell) |
| Pin 5 | I/O — Bidirectional I/O (macrocell) |
| Pin 6 | I/O — Bidirectional I/O (macrocell) |
| Pin 7 | I/O — Bidirectional I/O (macrocell) |
| Pin 8 | I/O — Bidirectional I/O (macrocell) |
| Pin 9 | INPUT — Dedicated input pin |
| Pin 10 | GND — Ground |
| Pin 11 | INPUT — Dedicated input pin |
| Pin 12 | I/O — Bidirectional I/O (macrocell) |
| Pin 13 | I/O — Bidirectional I/O (macrocell) |
| Pin 14 | I/O — Bidirectional I/O (macrocell) |
| Pin 15 | I/O — Bidirectional I/O (macrocell) |
| Pin 16 | I/O — Bidirectional I/O (macrocell) |
| Pin 17 | I/O — Bidirectional I/O (macrocell) |
| Pin 18 | I/O — Bidirectional I/O (macrocell) |
| Pin 19 | I/O — Bidirectional I/O (macrocell) |
| Pin 20 | I/O — Bidirectional I/O (macrocell) |
| Pin 21 | I/O — Bidirectional I/O (macrocell) |
| Pin 22 | INPUT — Dedicated input pin |
| Pin 23 | INPUT — Dedicated input pin |
| Pin 24 | VCC — 5 V supply |
Typical Applications
EP610PC-25 is suitable for 6 applications: 5 V Microprocessor Glue Logic, Address Decoding and Chip-Select Generation, ISA / Legacy Bus Peripheral Controller, Custom State Machine Controller, VGA / Video Timing Generator (Legacy), Legacy Peripheral Interface (Centronics / GPIB).
5 V Microprocessor Glue Logic
Replaces 74LS-series discrete gates with a single 24-pin EPLD in 8086/8051/Z80 microprocessor systems. The EP610PC-25's 16 macrocells at 25 ns tpd consolidate address decoding, chip-select generation, and bus-control logic; using external clock division. The 5 V Vcc and CMOS inputs are directly compatible with TTL-level buses, and the PDIP-24 footprint is socket-friendly for prototype boards and legacy industrial-control retrofits that retain through-hole assembly.
Recommended
Address Decoding and Chip-Select Generation
Generates chip-select signals for memory and peripheral banks from a CPU address bus. The EP610PC-25's 16 macrocells can decode up to 16 separate chip-select regions when configured as combinatorial outputs, each with programmable polarity. The 25 ns tpd adds minimal latency to the CPU memory-access cycle, and the shared sum-term structure across each 16x8 block is well matched to wide-input address decoding without burning macrocell feedback paths.
Recommended
ISA / Legacy Bus Peripheral Controller
Implements custom ISA-bus peripheral controllers for legacy PC/104 and embedded computing platforms. The EP610PC-25's PAL-type AND/OR plane plus per-macrocell flip-flop easily implements I/O decoding, interrupt acknowledge, and DMA handshake logic for 8-bit and 16-bit ISA cards. Pipelined data rates up to 100 MHz comfortably exceed the 8 MHz ISA bus clock, and the 5 V CMOS interface is TTL-compatible with the bus transceiver logic.
Recommended
Custom State Machine Controller
Implements custom finite-state machines (FSMs) for industrial automation, motor-control sequencers, and protocol converters. Each EP610PC-25 macrocell supports D, T, JK, or SR flip-flops with asynchronous clocking, allowing one-hot, binary, or Johnson-counter state encodings without external flip-flop packages. The 33 product terms per macrocell and shared sum terms support wide-decoded next-state logic, while the 25 ns tpd enables cycle times down to ~40 MHz in registered designs.
Recommended
VGA / Video Timing Generator (Legacy)
Generates horizontal and vertical sync signals for legacy VGA, CGA, and MDA video timing in industrial displays and retro-computing projects. The EP610PC-25's 16 macrocells provide enough register density to implement horizontal-sync, vertical-sync, and blanking counters in one device, and the 25 ns tpd supports pixel clock rates up to 40 MHz. The PDIP-24 through-hole package is also convenient for retro hobby builds that use through-hole construction techniques.
Recommended
Legacy Peripheral Interface (Centronics / GPIB)
Implements parallel-port handshaking for Centronics, GPIB, and other legacy byte-parallel interfaces. The EP610PC-25 macrocells map cleanly onto strobe/ack/busy handshake sequences and per-pin output-enable control, while the PAL-type AND/OR plane handles the wide-input status-decoding logic. The 5 V TTL-compatible I/O and 25 ns propagation delay meet the timing margins of legacy IEEE-488 and Centronics implementations without external logic.
Recommended
Recommended Products Summary
Engineering reference data for EP610PC-25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610PC-20 | EP610PC-15 | EP610PC-25T | EP610LI-25 | EP610DC-25 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PDIP-24 | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same | LCC-24 - same die, different footprint | CDIP-24 - same die, ceramic package |
| Propagation Delay (tpd) | 25 ns | 20 ns | 15 ns | 25 ns | 25 ns | 25 ns |
| Macro Cells | 16 | 16 | 16 | 16 | 16 | 16 |
| Usable Gates | 300 | 300 | 300 | 300 | 300 | 300 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM | CMOS EPROM | CMOS EPROM | CMOS EPROM | CMOS EPROM |
| Temperature Grade | Commercial | Commercial | Commercial | Commercial | Industrial | Military |
Key Differentiators
- Faster -20 and -15 speed grades are pin-compatible upgrades (vs EP610PC-20)
- Same die available in ceramic/military packages for harsh environments (vs EP610DC-25)
- Surface-mount LCC variant for SMT assembly (vs EP610LI-25)
Design Notes
Estimated macrocell usage: a single EP610PC-25 contains 16 macrocells in 4 blocks of 4, with 33 product terms each plus shared sum terms. Plan your AND-OR fit carefully - wide-input combinatorial functions can burn sum terms shared across the block, forcing you to redesign with fewer but wider decoders. Use Altera MAX+PLUS II compilation reports to verify that no resources are overcommitted before programming the device.
Estimated: at 5 V Vcc and 40 MHz toggle rate, the EP610PC-25 draws approximately 50-80 mA ICC depending on output loading and macrocell switching. Decouple Vcc with a 0.1 uF ceramic cap placed within 5 mm of the Vcc pin (pin 24) and a bulk 10 uF tantalum or aluminum cap on the same supply rail. Programmed EP610 devices draw standby current of a few mA; add a series ferrite bead if Vcc feeds noise-sensitive analog circuitry.
PDIP-24 sockets are strongly recommended for prototyping and field-replacement - the EP610PC-25 is a UV-erasable EPROM, so in-circuit reprogramming requires removal of the part. Use a low-profile machined-pin socket (e.g., 3M 2400 series) for reliable contacts. Keep clock-input traces short and away from I/O switching lines to minimize ground bounce on the 5 V TTL-level outputs.
Compliance Information
EP610PC-25 was designed before RoHS took effect; remaining stock is typically lead-bearing PDIP. Compliance status not documented in verified distributor data - source only from distributors who explicitly certify RoHS status if compliance is required.
