EP610PC-25 vs EP610PC-15 Comparison
Detailed side-by-side comparison of EP610PC-25 by Altera and EP610PC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-25 | EP610PC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $17.50 |
| Device Family | Classic EPLD (EP610 series) | β |
| Macro Cells | 16 | β |
| Usable Gates | 300 | 300 gates |
| Propagation Delay (tpd) | 25 ns | β |
| Maximum Pipelined Data Rate | 100 MHz | β |
| Supply Voltage (Vcc) | 5 V (nominal) | β |
| Technology | CMOS, EPROM (UV-erasable) | CMOS |
| Device Type | OT PLD, PAL-type, CMOS | EPLD (Erasable Programmable Logic Device) |
| Dedicated Inputs | 4 | β |
| I/O Pins | 20 (bidirectional, JTAG-programmable OE per macrocell) | β |
| Package | PDIP-24 (0.3 inch, through-hole) | PDIP-24 (plastic DIP, 24-pin) |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: operating temperature range] |
| Programming Method | EPROM (UV-erasable), via Altera programming hardware | β |
| Mounting Type | Through-Hole (DIP) | Through-Hole (DIP) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Family | β | Classic EPLD |
| Macrocells | β | 16 |
| Logic Delay (tPD) | β | 15 ns (pin-to-pin, -15 speed grade) |
| Maximum Counter Frequency | β | 100 MHz (per family datasheet) |
| Pipelined Data Rate | β | Up to 100 MHz |
| Supply Voltage (VCC) | β | 5 V (single supply) |
| Architecture | β | PAL-type, sum-of-products AND/OR array |
| TTL Emulation | β | 100% TTL compatible |
| Pin Count | β | 24 pins |
| Development Tool | β | Altera MAX+PLUS II |
| Logic Test Circuitry | β | On-board for AC/DC verification |