EP610PC-25 vs EP610PC-20 Comparison
Detailed side-by-side comparison of EP610PC-25 by Altera and EP610PC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-25 | EP610PC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $47.80 |
| Device Family | Classic EPLD (EP610 series) | β |
| Macro Cells | 16 | β |
| Usable Gates | 300 | 300 |
| Propagation Delay (tpd) | 25 ns | β |
| Maximum Pipelined Data Rate | 100 MHz | β |
| Supply Voltage (Vcc) | 5 V (nominal) | β |
| Technology | CMOS, EPROM (UV-erasable) | β |
| Device Type | OT PLD, PAL-type, CMOS | β |
| Dedicated Inputs | 4 | β |
| I/O Pins | 20 (bidirectional, JTAG-programmable OE per macrocell) | β |
| Package | PDIP-24 (0.3 inch, through-hole) | PDIP-24 |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | 0C to +70C (commercial) |
| Programming Method | EPROM (UV-erasable), via Altera programming hardware | β |
| Mounting Type | Through-Hole (DIP) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (legacy PDIP) |
| Family | β | Classic EPLD |
| Logic Elements | β | 16 macrocells |
| Propagation Delay (tPD) | β | 20 ns |
| Maximum Operating Frequency | β | 100 MHz (pipelined) |
| Supply Voltage (VCC) | β | 5 V Β±10% |
| Number of Pins | β | 24 |
| Process Technology | β | CMOS EPROM |
| Programmable Flip-Flops | β | 16 |
| Input Pins | β | 24 |
| Output Pins | β | 16 |
| I/O Compatibility | β | TTL |
| Program/Erase Method | β | UV (windowed) or OTP |