EP610PC-25T vs EP610DC-25 Comparison
Detailed side-by-side comparison of EP610PC-25T by Intel and EP610DC-25 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T β Last Time BuyRochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 β ActiveSpecification Comparison
| Parameter | EP610PC-25T | EP610DC-25 |
|---|---|---|
| Brand | Intel | Rochester Electronics |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $28.95 | $9.95 |
| Manufacturer | Intel (formerly Altera) | β |
| Distributor / Stocking Source | Rochester Electronics, LLC | β |
| Device Family | Altera Classic EPLD - EP610 | β |
| Device Type | Erasable Programmable Logic Device (EPLD, OTP for plastic package) | β |
| Logic Capacity | 300 usable gates | β |
| Macro Cells | 16 | β |
| Registers | 16 | β |
| User I/Os | 16 | β |
| Propagation Delay (tPD) | 25 ns (speed grade 25) | β |
| Maximum Toggle Frequency | [DATA_NEEDED: max fmax] | β |
| Pipelined Data Rate | up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | ECMOS (CMOS, EPROM-based) | β |
| Package | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) | 24-pin CDIP (Ceramic DIP, through-hole) |
| Pinout Compatibility | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) | β |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial) | 0 C to +70 C |
| Programming Method | OTP (one-time programmable) via Altera programming hardware | JEDEC fuse-map / UV-erase |
| Mounting Type | Through-hole | Through Hole |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Shipping Form (T suffix) | Tube | β |
| Family | β | Altera Classic EPLD |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Macrocells | β | 16 |
| Equivalent Gates | β | 300 |
| Maximum Propagation Delay (tPD) | β | 25 ns |
| Number of I/O Pins | β | 22 |
| Number of Dedicated Inputs | β | 4 |
| Total Pin Count | β | 24 |
| Technology | β | CMOS EPROM (UV-erasable) |
| Speed Grade Suffix | β | -25 (25 ns tPD) |