EP610PC-30 vs EP610PC-15 Comparison
Detailed side-by-side comparison of EP610PC-30 by Altera and EP610PC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-30 | EP610PC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $27.74 | $17.50 |
| Device Family | Classic EPLD (EP610) | β |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 gates |
| Propagation Delay (tPD) | 30 ns | β |
| Maximum Pipeline Frequency | 33.3 MHz (typical) / 100 MHz pipelined | β |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V (single supply) |
| Process Technology | CMOS EPROM | β |
| Package | 24-pin PDIP (0.300 inch) | PDIP-24 (plastic DIP, 24-pin) |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| Programmability | One-Time Programmable (OTP, no window on plastic PDIP) | β |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Output Drive Current | [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] | β |
| Input Pins (Dedicated) | [DATA_NEEDED: dedicated input count from datasheet pinout] | β |
| I/O Pins | [DATA_NEEDED: bidirectional I/O count from datasheet pinout] | β |
| Programming Tool | Altera A+PLUS / MAX+PLUS II (legacy) | β |
| RoHS Status | Not applicable (legacy non-compliant package per distributor listing) | [DATA_NEEDED: RoHS status] |
| Lead Free Status | Not applicable | β |
| Current Distributor | Rochester Electronics, LLC (authorized continuing source) | β |
| Family | β | Classic EPLD |
| Device Type | β | EPLD (Erasable Programmable Logic Device) |
| Logic Delay (tPD) | β | 15 ns (pin-to-pin, -15 speed grade) |
| Maximum Counter Frequency | β | 100 MHz (per family datasheet) |
| Pipelined Data Rate | β | Up to 100 MHz |
| Technology | β | CMOS |
| Architecture | β | PAL-type, sum-of-products AND/OR array |
| TTL Emulation | β | 100% TTL compatible |
| Pin Count | β | 24 pins |
| Development Tool | β | Altera MAX+PLUS II |
| Logic Test Circuitry | β | On-board for AC/DC verification |