EP610PC-30 - 16-Macrocell Classic EPLD, 30ns, PDIP-24 | Altera
MPN: EP610PC-30 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $27.74 | $27.74 |
| 5 | $60.53 | $302.65 |
| 10 | $55 | $550.00 |
| 100 | $45 | $4,500.00 |
| 500 | $38 | $19,000.00 |
EP610PC-30 Overview
Classic EPLDs are a category of programmable logic devices (semiconductors) that combine AND/OR array logic with user-programmable macrocells. The Classic EPLD sits hierarchically within: programmable logic -> PLD -> EPLD -> Classic EPLD -> CMOS erasable PLD. Compared to earlier PAL/GAL devices, Classic EPLDs add output macrocells with configurable registers, feedback paths, and product-term allocation, enabling integration of multiple PAL-equivalent functions into a single chip.
Key specifications of the EP610PC-30 include 300 usable gates, 16 macrocells, a 30 ns pin-to-pin propagation delay (tPD), a 33.3 MHz maximum pipeline frequency, and 5 V CMOS operation. The device supports asynchronous or synchronous clocking with dedicated input pins, provides 24 mA drive on outputs (typical), and is housed in a 24-pin 0.300-inch PDIP (Plastic Dual In-line Package) with through-hole mounting suitable for breadboarding, legacy retrofits, and industrial control equipment.
The EP610PC-30 is fabricated in a 1-micron CMOS EPROM process with a quartz window option (not present on the plastic package). The architecture centers on a programmable AND array feeding an OR array into 16 output macrocells, each with a programmable register, output enable, and feedback path. Programming is performed with a standard EPROM programmer using the Altera A+PLUS or MAX+PLUS II toolchain (legacy software). The device is one-time programmable when supplied in the plastic PDIP package without a window.
Typical applications include glue logic replacement for discrete 74-series TTL/CMOS gates, address decoding for 8-bit and 16-bit microprocessor systems, state-machine implementation for industrial controllers, bus-interface arbitration in legacy PC/104 and VME systems, and I/O decoding in M68000, x86, or 8051-based designs. Designers continue to use the EP610 family for long-lifecycle industrial, military, and aerospace programs where re-spinning a PCB around a modern CPLD is not feasible.
When designing with this part, ensure the 30 ns tPD is compatible with the target system clock - it suits 8-25 MHz bus architectures. The device requires a single 5 V supply; a 0.1 uF decoupling capacitor placed close to VCC pin 24 is recommended. Because the EP610PC-30 is a mature product, long-lead-time planning and authorized stocking distributors should be considered for production runs.
This page synthesizes Rochester Electronics distributor pricing, package-level technical data, same-family Altera EPLD drop-in alternatives, and design guidance that goes beyond what the original manufacturer datasheet alone offers.
Drop-in alternatives for EP610PC-30 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610PC-30 (same form factor and footprint) β differing in Package, Supply Voltage (VCC), Propagation Delay (tPD), Technology, Operating Temperature.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP610PC-25
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEP610PC-20
β Drop-Inβ In Stock
$47.8 / Unit
View Datasheet βEP610PC-15
β Drop-Inβ In Stock
$17.5 / Unit
View Datasheet βEP610DC-30
β Drop-Inβ In Stock
$10.4 / Unit
View Datasheet βEP610PC-20T
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$7.2 / Unit
View Datasheet βEP610PC-25T
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$28.95 / Unit
View Datasheet βEP610PC-30 Maximum Ratings & Electrical Characteristics
| Device Family | Classic EPLD (EP610) |
| Macrocells | 16 |
| Usable Gates | 300 |
| Propagation Delay (tPD) | 30 ns |
| Maximum Pipeline Frequency | 33.3 MHz (typical) / 100 MHz pipelined |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) |
| Process Technology | CMOS EPROM |
| Package | 24-pin PDIP (0.300 inch) |
| Mounting Type | Through-Hole |
| Programmability | One-Time Programmable (OTP, no window on plastic PDIP) |
| Operating Temperature | 0C to +70C (commercial) |
| Programming Tool | Altera A+PLUS / MAX+PLUS II (legacy) |
| RoHS Status | Not applicable (legacy non-compliant package per distributor listing) |
| Lead Free Status | Not applicable |
| Current Distributor | Rochester Electronics, LLC (authorized continuing source) |
EP610PC-30 Pin Configuration
| Pin 1 | I/O β Bidirectional I/O pin (function per macrocell assignment) |
| Pin 2 | I/O β Bidirectional I/O pin |
| Pin 3 | I/O β Bidirectional I/O pin |
| Pin 4 | I/O β Bidirectional I/O pin |
| Pin 5 | I/O β Bidirectional I/O pin |
| Pin 6 | I/O β Bidirectional I/O pin |
| Pin 7 | I/O β Bidirectional I/O pin |
| Pin 8 | β Bidirectional I/O pin |
| Pin 9 | I/O β Bidirectional I/O pin |
| Pin 10 | I/O β Bidirectional I/O pin |
| Pin 11 | INPUT β Dedicated input pin |
| Pin 12 | GND β Ground |
| Pin 13 | INPUT β Dedicated input pin |
| Pin 14 | INPUT β Dedicated input pin |
| Pin 15 | INPUT β Dedicated input pin |
| Pin 16 | CLK β Global clock input |
| Pin 17 | OE β Output enable (global or per-macrocell) |
| Pin 18 | I/O β Bidirectional I/O pin |
| Pin 19 | I/O β Bidirectional I/O pin |
| Pin 20 | I/O β Bidirectional I/O pin |
| Pin 21 | I/O β Bidirectional I/O pin |
| Pin 22 | I/O β Bidirectional I/O pin |
| Pin 23 | I/O β Bidirectional I/O pin |
| Pin 24 | VCC β +5 V supply |
Typical Applications
EP610PC-30 is suitable for 6 applications: Glue Logic Replacement for 74-series TTL, Address Decoding for 8/16-bit Microprocessor Systems, State Machine Implementation in Industrial Controllers, Bus Interface Arbitration in PC/104 and VME Systems, I/O Decoding in M68000, x86, and 8051 Designs, Legacy Industrial Retrofit and Long-Lifecycle Programs.
Glue Logic Replacement for 74-series TTL
The EP610PC-30 is widely used as glue-logic consolidation, replacing dozens of 74LS00/74HC/74F-series gates on legacy boards. With 16 macrocells providing 300 usable gates, a single EP610PC-30 can absorb multiple discrete packages - reducing PCB area, lowering BOM count, and improving reliability by eliminating inter-chip wiring. The 30 ns tPD matches 74LS-series speed (typical tPD 9-15 ns for individual gates, 30 ns for multi-level paths), making timing drop-in compatible with existing 74LS-based schematics. The 5 V CMOS supply also matches TTL rails directly. Designers port 74-series logic by mapping each gate cluster into one macrocell using AHDL or schematic entry in MAX+PLUS II, and program the chip once on the production line.
Recommended
Address Decoding for 8/16-bit Microprocessor Systems
Address-decoding PLDs are a core use case for the EP610PC-30 in 8051, Z80, 68HC11, 8086, and 68000-based designs. The 16 macrocells can decode up to 16 separate chip-select outputs from a single chip, each implementing a custom address map for memory, I/O, or peripheral devices. The 30 ns tPD sits within one clock cycle at 8-25 MHz bus speeds, satisfying setup-time requirements for downstream peripherals without wait states. Outputs can be configured as active-high or active-low with configurable polarity, eliminating the need for external inverters. The device also supports registered outputs for synchronous bus designs where chip-select must align to clock edges. The PDIP-24 package suits through-hole prototype boards common in industrial controller retrofits.
Recommended
State Machine Implementation in Industrial Controllers
The EP610PC-30 is well-suited to small-to-medium state machines controlling relays, motors, solenoids, and indicators in industrial automation. Each macrocell can implement one FSM state with registered output, and the 16 macrocells comfortably handle FSMs up to 16 states - covering most conveyor, valve-sequencing, and process-control applications. Registered macrocell outputs provide clean synchronous transitions without glitches, critical for safety-relevant control logic. The 5 V CMOS supply is noise-tolerant in factory environments, and the 0-70C commercial temperature range covers most indoor cabinets. Designers encode the FSM in AHDL or schematic capture and lock the design into the OTP EPROM, eliminating firmware-update risk in the field.
Recommended
Bus Interface Arbitration in PC/104 and VME Systems
Bus-arbitration logic in legacy PC/104, VME, and STD-bus systems relies on PLDs to handle request/grant handshakes, address mapping, and interrupt prioritization. The EP610PC-30's 16 macrocells can implement a complete bus arbiter for up to 8 masters with daisy-chain priority, plus interrupt acknowledge logic, plus address-decoding - replacing 4-6 discrete PALs on the original schematics. The 30 ns tPD provides clean arbitration timing at 8 MHz PC/104 bus speeds without metastability issues. The PDIP-24 package is compatible with legacy through-hole PCBs that cannot accept SMD CPLDs without redesign. Rochester Electronics' continuing-source program ensures multi-year supply for long-lifecycle military and aerospace programs still using PC/104 and VMEbus.
Recommended
I/O Decoding in M68000, x86, and 8051 Designs
I/O port decoding is one of the most cost-effective uses of the EP610PC-30, replacing multiple 74LS138/139 decoder ICs with a single programmable device. Each macrocell output drives one chip-select line for an I/O peripheral - covering UARTs, timers, parallel ports, ADC/DAC chips, and memory-mapped registers. With 16 macrocells, designers can implement a complete I/O map for systems with up to 16 peripherals, leaving the address bus free for memory expansion. The 30 ns tPD fits the I/O access timing for 8-bit 8051 (12 MHz, 1 us cycle) and 16-bit x86 (8 MHz AT-bus) without wait states. Polarity-configurable outputs eliminate the need for external inverters common with 74LS138 designs.
Recommended
Legacy Industrial Retrofit and Long-Lifecycle Programs
The EP610PC-30 remains in demand for long-lifecycle industrial, military, and aerospace programs where re-spinning a PCB around a modern CPLD is cost-prohibitive. Examples include 1980s-era CNC controllers, factory-floor PLCs, military radios, avionics subsystems, and railway signaling equipment, all of which still use EP610-family PLDs in production. Rochester Electronics is the authorized continuing-source supplier, providing factory-traceable parts and multi-year scheduled supply agreements. The 30 ns tPD and 5 V supply are exact drop-in for the original 1985-1995 designs. Designers maintaining these systems can stock EP610PC-30 and the speed-grade variants (EP610PC-25, EP610PC-20) to cover field replacements for the next 10-20 years.
Recommended
Recommended Products Summary
Engineering reference data for EP610PC-30 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610PC-25 | EP610PC-20 | EP610PC-15 | EP610DC-30 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | 24-pin PDIP (0.300 in) | 24-pin PDIP (0.300 in) - same | 24-pin PDIP (0.300 in) - same | 24-pin PDIP (0.300 in) - same | 24-pin CERDIP (windowed) - same pin count, different package material |
| Propagation Delay (tPD) | 30 ns | 25 ns | 20 ns | 15 ns | 30 ns |
| Macrocells | 16 | 16 | 16 | 16 | 16 |
| Usable Gates | 300 | 300 | 300 | 300 | 300 |
| Supply Voltage | 5 V (4.75-5.25 V) | 5 V | 5 V | 5 V | 5 V |
| Programmability | OTP (no UV window) | OTP | OTP | OTP | Windowed (UV-erasable) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C |
| Lifecycle Status | NRND (Rochester continuing) | NRND | NRND | NRND | NRND |
Key Differentiators
- Drop-in speed upgrade available with zero PCB change (vs EP610PC-25)
- Windowed CERDIP option for design iteration (vs EP610DC-30)
- Maximum speed available in 24-pin PDIP for high-frequency legacy bus (vs EP610PC-15)
Design Notes
Estimated: at 5 V VCC and all 16 macrocells toggling at 33.3 MHz, the EP610PC-30 draws roughly 100-300 mA depending on output loading. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of pin 24 (VCC), and add a 10 uF bulk tantalum or aluminum electrolytic capacitor near the device for transient suppression. The CMOS EPROM core draws negligible standby current. Ensure the 5 V rail has < 100 mVpp ripple to avoid timing jitter at high toggle rates.
Do NOT assume any I/O pin can be a dedicated input or a registered output without checking your compiled design report. Classic EPLDs assign I/O direction and register usage via the fitter - always review the pinout report after compilation. Also note: the EP610PC-30 (plastic PDIP) is one-time programmable; there is NO UV window for erasure. If you need to iterate the design, use a CERDIP-windowed variant (EP610DC-30) on the bench and port the final JEDEC file to the production OTP device.
Keep the EP610PC-30 away from switching power converters and high-current traces to avoid noise coupling into the analog VCC rail. For 5 V designs, the EP610PC-30 should share a clean digital 5 V rail - not a rail shared with motors or relays. Place ground-return vias within 2 mm of GND pin 12. For through-hole PDIP-24 sockets (e.g., Mill-Max 110-44-624-41-001000) for prototype iteration, add 100 nF bypass on each socket-side VCC pin if used in a high-noise environment.
Compliance Information
Per distributor listings (integrated-circuit-ics.com, lcsc.com), RoHS Status and Lead Free Status are 'Not applicable' for EP610PC-30 because it is a legacy non-compliant package supplied for maintenance of legacy systems. Rochester Electronics is the authorized continuing-source supplier.
