EP610PC-30 vs EP610PC-20 Comparison
Detailed side-by-side comparison of EP610PC-30 by Altera and EP610PC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-30 | EP610PC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $27.74 | $47.80 |
| Device Family | Classic EPLD (EP610) | β |
| Macrocells | 16 | β |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 30 ns | 20 ns |
| Maximum Pipeline Frequency | 33.3 MHz (typical) / 100 MHz pipelined | β |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V Β±10% |
| Process Technology | CMOS EPROM | CMOS EPROM |
| Package | 24-pin PDIP (0.300 inch) | PDIP-24 |
| Mounting Type | Through-Hole | β |
| Programmability | One-Time Programmable (OTP, no window on plastic PDIP) | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Output Drive Current | [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] | β |
| Input Pins (Dedicated) | [DATA_NEEDED: dedicated input count from datasheet pinout] | β |
| I/O Pins | [DATA_NEEDED: bidirectional I/O count from datasheet pinout] | β |
| Programming Tool | Altera A+PLUS / MAX+PLUS II (legacy) | β |
| RoHS Status | Not applicable (legacy non-compliant package per distributor listing) | Non-compliant (legacy PDIP) |
| Lead Free Status | Not applicable | β |
| Current Distributor | Rochester Electronics, LLC (authorized continuing source) | β |
| Family | β | Classic EPLD |
| Logic Elements | β | 16 macrocells |
| Maximum Operating Frequency | β | 100 MHz (pipelined) |
| Number of Pins | β | 24 |
| Programmable Flip-Flops | β | 16 |
| Input Pins | β | 24 |
| Output Pins | β | 16 |
| I/O Compatibility | β | TTL |
| Program/Erase Method | β | UV (windowed) or OTP |