EP610PC-30 vs EP610PC-25 Comparison

Detailed side-by-side comparison of EP610PC-30 by Altera and EP610PC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP610PC-30 EP610PC-25
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $27.74 $9.75
Device Family Classic EPLD (EP610) Classic EPLD (EP610 series)
Macrocells 16 β€”
Usable Gates 300 300
Propagation Delay (tPD) 30 ns β€”
Maximum Pipeline Frequency 33.3 MHz (typical) / 100 MHz pipelined β€”
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) β€”
Process Technology CMOS EPROM β€”
Package 24-pin PDIP (0.300 inch) PDIP-24 (0.3 inch, through-hole)
Mounting Type Through-Hole Through-Hole (DIP)
Programmability One-Time Programmable (OTP, no window on plastic PDIP) β€”
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: operating temperature grade]
Output Drive Current [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] β€”
Input Pins (Dedicated) [DATA_NEEDED: dedicated input count from datasheet pinout] β€”
I/O Pins [DATA_NEEDED: bidirectional I/O count from datasheet pinout] 20 (bidirectional, JTAG-programmable OE per macrocell)
Programming Tool Altera A+PLUS / MAX+PLUS II (legacy) β€”
RoHS Status Not applicable (legacy non-compliant package per distributor listing) [DATA_NEEDED: RoHS status]
Lead Free Status Not applicable β€”
Current Distributor Rochester Electronics, LLC (authorized continuing source) β€”
Macro Cells β€” 16
Propagation Delay (tpd) β€” 25 ns
Maximum Pipelined Data Rate β€” 100 MHz
Supply Voltage (Vcc) β€” 5 V (nominal)
Technology β€” CMOS, EPROM (UV-erasable)
Device Type β€” OT PLD, PAL-type, CMOS
Dedicated Inputs β€” 4
Programming Method β€” EPROM (UV-erasable), via Altera programming hardware

Datasheets & Resources

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