EP610PI-25 vs EP610DC-25 Comparison
Detailed side-by-side comparison of EP610PI-25 by Rochester Electronics and EP610DC-25 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610PI-25 - 16-Macrocell Classic EPLD, 25ns DIP-24 | Rochester
EP610PI-25 ObsoleteRochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 β ActiveSpecification Comparison
| Parameter | EP610PI-25 | EP610DC-25 |
|---|---|---|
| Brand | Rochester Electronics | Rochester Electronics |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $20.50 | $9.95 |
| Product Type | Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Series | Classic EP610 | β |
| Macrocells | 16 | 16 |
| Usable Gates | ~300 gates | β |
| Propagation Delay (tPD) | 25 ns | β |
| Maximum Internal Frequency (fCNT) | [DATA_NEEDED: fCNT] | β |
| Number of Dedicated Inputs | 4 | 4 |
| Number of Bidirectional I/O Pins | 16 | β |
| Package | 24-pin DIP (PI) ceramic through-hole | 24-pin CDIP (Ceramic DIP, through-hole) |
| Operating Temperature Range | Industrial (I suffix): -40C to +85C | β |
| Supply Voltage (VCC) | 5 V nominal | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | CMOS, UV-erasable | β |
| Programmable Flip-Flop Modes | D, T, JK, SR (per macrocell) | β |
| Global Clock Pins | 1 | β |
| Mounting Type | Through-Hole (DIP) | Through Hole |
| Lead-Free / RoHS | [DATA_NEEDED: RoHS] | β |
| Original Manufacturer | Altera (now Intel PSG; legacy stock from Rochester Electronics) | β |
| Family | β | Altera Classic EPLD |
| Equivalent Gates | β | 300 |
| Maximum Propagation Delay (tPD) | β | 25 ns |
| Pipelined Data Rate | β | Up to 100 MHz |
| Number of I/O Pins | β | 22 |
| Total Pin Count | β | 24 |
| Operating Temperature | β | 0 C to +70 C |
| Technology | β | CMOS EPROM (UV-erasable) |
| Programming Method | β | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | β | -25 (25 ns tPD) |