EP610PI-25 - 16-Macrocell Classic EPLD, 25ns DIP-24 | Rochester
MPN: EP610PI-25 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $30.08 | $30.08 |
| 10 | $28.5 | $285.00 |
| 100 | $25.2 | $2,520.00 |
| 500 | $22.8 | $11,400.00 |
| 1,000 | $20.5 | $20,500.00 |
EP610PI-25 Overview
A Programmable Logic Device (PLD) is a general-purpose digital IC whose logic function is defined after manufacture by the user, sitting in the broader hierarchy of programmable logic between simple PAL/GAL arrays and modern CPLD/FPGA fabrics. The Classic EP610 family represents an early generation of CMOS UV-erasable EPLDs that consolidated several PAL-equivalent macrocells into a single AND/OR array with per-macrocell flip-flop and output enable control. The 'P' suffix designates the plastic/ceramic DIP package, the 'I' indicates the industrial operating temperature range, and the '-25' suffix specifies the 25 ns tPD speed grade, which is the slowest of the family and well suited to bus-interface and control-logic applications running below ~40 MHz.
Key features of the EP610PI-25 include 16 macrocells, four dedicated inputs, 16 bidirectional I/O pins in the 24-pin DIP, output macrocell flip-flops with configurable D/T/JK/SR modes, programmable output enable per macrocell, and a single global clock. Architecture is based on a sum-of-products (AND-OR) PLA with each macrocell feeding one bidirectional I/O pin. The device is non-volatile (UV-erasable) and offers deterministic 25 ns propagation delay that does not depend on routing density, an advantage over later channel-routed CPLDs. Power consumption is typically under 200 mW at 5 V, and the part is 100% pin-compatible with the EP610PI-20 and EP610PI-15 faster speed grades, allowing direct in-circuit speed upgrade.
Typical applications include legacy bus-interface decoding (8086, 68000, Z80 address decode and glue logic), industrial control state machines, telecommunications channel-bank control, instrumentation address decoding, and as a pin-compatible replacement for multiple PAL/GAL devices in legacy aerospace and military systems. The DIP-24 through-hole footprint also supports easy breadboarding and socketed replacement in maintenance scenarios.
When designing with the EP610PI-25, use the Altera MAX+PLUS II (legacy) or A+PLUS development environment for schematic/VHDL/Verilog entry, and ensure the JTAG/programming socket allows UV erasure (windowed packages). Provide a clean 5 V ±5% supply and decouple VCC with a 0.1 µF ceramic capacitor adjacent to the IC. Note that modern 5 V-tolerant CPLDs such as the MAX II family offer much higher density but at a different pinout; the EP610PI-25 is a true drop-in for legacy EP610 designs only.
This page synthesizes legacy Rochester Electronics distributor pricing, drop-in EP610 family alternatives that share the DIP-24 footprint, and practical design notes for maintaining legacy EPLD designs not found in the original Altera datasheet.
Drop-in alternatives for EP610PI-25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610PI-25 (same form factor and footprint) — differing in Package, Family, Technology, Mounting Type, Supply Voltage (VCC).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610PC-25
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$9.75 / Unit
View Datasheet →EP610DC-25
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$9.95 / Unit
View Datasheet →EP610LC-25
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$6.2 / Unit
View Datasheet →EP610IPC-25
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$8.85 / Unit
View Datasheet →EP610PC-25T
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$28.95 / Unit
View Datasheet →EP610LI-25
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$17.25 / Unit
View Datasheet →EP610PI-25 Maximum Ratings & Electrical Characteristics
| Product Type | Erasable Programmable Logic Device (EPLD) |
| Series | Classic EP610 |
| Macrocells | 16 |
| Usable Gates | ~300 gates |
| Propagation Delay (tPD) | 25 ns |
| Number of Dedicated Inputs | 4 |
| Number of Bidirectional I/O Pins | 16 |
| Package | 24-pin DIP (PI) ceramic through-hole |
| Operating Temperature Range | Industrial (I suffix): -40C to +85C |
| Supply Voltage (VCC) | 5 V nominal |
| Process Technology | CMOS, UV-erasable |
| Programmable Flip-Flop Modes | D, T, JK, SR (per macrocell) |
| Global Clock Pins | 1 |
| Mounting Type | Through-Hole (DIP) |
| Original Manufacturer | Altera (now Intel PSG; legacy stock from Rochester Electronics) |
EP610PI-25 Pin Configuration
| Pin 1 | I/O0 — Bidirectional I/O / macrocell 0 (with input and feedback) |
| Pin 2 | I/O1 — Bidirectional I/O / macrocell 1 |
| Pin 3 | I/O2 — Bidirectional I/O / macrocell 2 |
| Pin 4 | I/O3 — Bidirectional I/O / macrocell 3 |
| Pin 5 | I/O4 — Bidirectional I/O / macrocell 4 |
| Pin 6 | I/O5 — Bidirectional I/O / macrocell 5 |
| Pin 7 | I/O6 — Bidirectional I/O / macrocell 6 |
| Pin 8 | I/O7 — Bidirectional I/O / macrocell 7 |
| Pin 9 | I/O8 — Bidirectional I/O / macrocell 8 |
| Pin 10 | I/O9 — Bidirectional I/O / macrocell 9 |
| Pin 11 | I/O10 — Bidirectional I/O / macrocell 10 |
| Pin 12 | GND — Ground |
| Pin 13 | I/O11 — Bidirectional I/O / macrocell 11 |
| Pin 14 | I/O12 — Bidirectional I/O / macrocell 12 |
| Pin 15 | I/O13 — Bidirectional I/O / macrocell 13 |
| Pin 16 | I/O14 — Bidirectional I/O / macrocell 14 |
| Pin 17 | I/O15 — Bidirectional I/O / macrocell 15 |
| Pin 18 | IN0 — Dedicated input 0 |
| Pin 19 | IN1 — Dedicated input 1 |
| Pin 20 | IN2 — Dedicated input 2 |
| Pin 21 | IN3 — Dedicated input 3 |
| Pin 22 | CLK — Global clock input |
| Pin 23 | OE — Global output enable (active low) |
| Pin 24 | VCC — +5 V supply |
Typical Applications
EP610PI-25 is suitable for 6 applications: Legacy 8086/68000 Bus Address Decoding, Industrial Control State Machines, Telecommunications Channel-Bank Control, Legacy Test & Measurement Instrumentation, Aerospace & Military Avionics Sustainment, Pin-Compatible PAL/GAL Array Consolidation.
Legacy 8086/68000 Bus Address Decoding
The EP610PI-25's 25 ns tPD and 16 macrocells make it ideal for legacy 8 MHz to 16 MHz microprocessor address-decoding and chip-select generation. In a typical 8086 system, the EPLD replaces four to six 74LS138/139/688 decoders by mapping the 20-bit address bus to chip enables for ROM, RAM, and I/O devices, reducing board area by ~60%. The 25 ns propagation delay easily fits within the 8 MHz 8086 memory-access window, while the ceramic DIP-24 (PI) package supports socketed replacement during board bring-up or field maintenance.
Recommended
Industrial Control State Machines
The EP610PI-25's per-macrocell D/T/JK/SR flip-flops and 16-macrocell capacity provide a clean implementation medium for industrial state machines controlling 8 to 16 outputs with 4 to 8 inputs. The industrial -40C to +85C operating range and DIP-24 through-hole footprint allow direct socketed insertion into PLC backplanes, motor-control boards, and process-instrumentation front-ends. The deterministic 25 ns tPD does not vary with routing density, simplifying worst-case timing analysis for safety-critical sequences such as conveyor interlocks and valve sequencing.
Recommended
Telecommunications Channel-Bank Control
The EP610PI-25 is well suited for telecom channel-bank control-logic applications where 5 V CMOS operation, industrial temperature range, and a 25 ns deterministic propagation delay satisfy channel-switch and signaling-rate requirements. The device replaces discrete 74HC logic implementing time-slot assignment, relay-driver control, and alarm-collection logic. Rochester Electronics' ongoing wafer-level manufacturing ensures multi-year supply continuity required by telecom operators maintaining T1/E1 infrastructure beyond standard end-of-life windows.
Recommended
Legacy Test & Measurement Instrumentation
The EP610PI-25's 5 V CMOS operation, 16 macrocells, and 25 ns deterministic delay are well matched to legacy bench-top oscilloscopes, logic analyzers, and protocol analyzers where it implements front-panel key-scan decoding, trigger conditioning, and timing-and-control glue between display drivers, ADC/DAC subsystems, and the main processor. The ceramic DIP-24 package allows socketed replacement during instrument calibration cycles, simplifying field service for equipment with 20+ year service lives.
Recommended
Aerospace & Military Avionics Sustainment
The EP610PI-25 and its military-grade counterpart EP610DM/883B support long-life aerospace and military avionics programs that must maintain form-fit-function compatibility with original equipment deployed in the 1980s and 1990s. The 24-pin ceramic DIP-24 (PI) footprint, industrial temperature range, and 25 ns tPD match the original Altera EP610 datasheet specifications exactly, allowing drop-in replacement on existing qualified boards without re-qualification. Rochester Electronics is the primary authorized source for these legacy military-grade EPLDs.
Recommended
Pin-Compatible PAL/GAL Array Consolidation
The EP610PI-25 is widely used to consolidate multiple 20-pin and 24-pin PAL/GAL devices into a single EPLD, simplifying PCB layout and reducing BOM count by 4x to 6x. The 16 macrocells map cleanly to four 16V8-equivalent devices or two 22V10-equivalent devices, with the 25 ns tPD matching typical bipolar PAL-20L8 and PAL-22V10 speed grades. Designers migrating from discrete PAL/GAL to EPLD benefit from reduced power consumption (~200 mW vs ~1.5 W total for bipolar PALs), single-device sourcing, and Rochester Electronics' long-term supply commitment.
Recommended
Recommended Products Summary
Engineering reference data for EP610PI-25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610PC-25 | EP610DC-25 | EP610LC-25 |
|---|---|---|---|---|
| Brand | Rochester Electronics (legacy Altera) | Rochester Electronics (legacy Altera) | Rochester Electronics (legacy Altera) | Rochester Electronics (legacy Altera) |
| Package | 24-pin DIP (PI) ceramic | 24-pin DIP (PI) plastic - same | 24-pin DIP (PI) windowed ceramic - same | 24-pin DIP (PI) windowed LCC - same pin-out |
| Propagation Delay (tPD) | 25 ns | 25 ns | 25 ns | 25 ns |
| Macrocells | 16 | 16 | 16 | 16 |
| Usable Gates | ~300 gates | ~300 gates | ~300 gates | ~300 gates |
| Operating Temperature Range | Industrial -40C to +85C | Commercial 0C to +70C | Military -55C to +125C | Military -55C to +125C |
| Package Material | Ceramic DIP | Plastic DIP | Ceramic DIP, UV-windowed | Ceramic LCC, UV-windowed |
| UV Erasable (Field Reprogrammable) | No (one-time-programmable OTP variant) | No (OTP) | Yes (windowed) | Yes (windowed) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V |
Key Differentiators
- Industrial temperature grade in 24-pin ceramic DIP (vs EP610PC-25)
- Original Altera EP610 die with Rochester authorized sourcing (vs Modern MAX II CPLDs (e.g., EPM240T100C5N))
- Deterministic 25 ns propagation delay independent of logic density (vs PAL20L8 / GAL22V10 bipolar devices)
Design Notes
The EP610PI-25 operates from a single 5 V ±5% supply and typically draws ~30 mA quiescent plus dynamic current proportional to switching frequency. Decouple VCC (pin 24) with a 0.1 µF ceramic capacitor placed within 5 mm of the package, plus a 10 µF tantalum bulk capacitor on the supply rail. The CMOS UV-erasable architecture has high noise immunity but the global clock input (pin 22) should be routed away from high-current switching traces to avoid ground-bounce-induced false clocking.
The EP610PI-25 is the OTP (one-time-programmable) non-windowed variant - once programmed, it cannot be UV-erased. For prototyping or designs that may require field firmware updates, choose EP610DC-25 or EP610LC-25 (windowed ceramic packages). Always verify the JEDEC programming file matches the socketed pin orientation; the DIP-24 pin 1 marker is the standard counter-clockwise numbering from the top-left notch. Programming must use legacy Altera MAX+PLUS II or A+PLUS software with the original EP610 JEDEC fuse map.
At ~200 mW typical dissipation in a ceramic DIP-24 package (theta_JA ~50 C/W in still air), the EP610PI-25 junction-to-ambient temperature rise is approximately 10 C above ambient. This is well within the industrial -40C to +85C operating range with no heatsinking required. Estimated: Pdiss=200 mW, theta_JA=50 C/W, delta_T=10 C. For military-temp EP610DC-25 / EP610LC-25 variants deployed in sealed enclosures, confirm worst-case ambient plus 10 C junction rise stays within the -55C to +125C military spec.
Compliance Information
EP610PI-25 is a 1980s-era Altera legacy EPLD; RoHS/REACH compliance status not explicitly documented in the available distributor data. For military/aerospace programs use EP610DM/883B (MIL-STD-883 qualified). Rochester Electronics is an authorized source for legacy Altera EPLDs and provides original-die equivalents.
