EP910DI-35 vs EP910DC-30 Comparison
Detailed side-by-side comparison of EP910DI-35 by Altera and EP910DC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DI-35 | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $35.20 | $15.60 |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Family | Altera Classic EPLD | Classic EPLD (EP910 series) |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | β |
| Propagation Delay (tPD) | 35 ns | 30 ns (max) |
| Maximum Toggle Frequency (fCNT) | 28.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | β |
| Supply Current (ICC) | 40 mA typical | β |
| Dedicated Inputs | 10 | 36 |
| Bidirectional I/O Pins | 20 | β |
| Total Pins | 40 | β |
| Package | CDIP-40 (Ceramic DIP with UV window) | DIP-40 (through-hole, 600 mil) |
| Mounting Type | Through-Hole | Through-Hole |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Technology | CMOS, UV-erasable EPROM | β |
| Programming Method | EPROM programmer + JEDEC fuse map | UV-Erasable / OTP |
| Erasure Method | UV light through quartz window | β |
| RoHS Status | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] | β |
| Logic Family | PAL-type AND/OR array with D flip-flops | β |
| Manufacturer | Original Altera; long-term authorized by Rochester Electronics, LLC | β |
| Architecture | β | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | β | 900 usable gates |
| Clock Frequency (fCNT) | β | 33.3 MHz |
| Outputs (Macrocells) | β | 24 |
| External Clock Pins | β | 2 (CLK1, CLK2) |
| Supply Voltage | β | 5 V |
| Process Technology | β | CMOS |