EP910ILC-25 vs EP910ILC-50 Comparison
Detailed side-by-side comparison of EP910ILC-25 by Intel and EP910ILC-50 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910ILC-25 | EP910ILC-50 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $10.85 |
| Family | EP910 Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | 24 |
| Propagation Delay (tPD) | 25 ns | β |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | β |
| Logic Blocks | Sum-of-products AND/OR array | β |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM, UV-erasable |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | β |
| Package | 44-pin JLCC (windowed ceramic) | PLCC-44 (J-lead) |
| Mounting Type | Surface Mount | Surface Mount (socket-compatible) |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Supply Voltage | 5 V | β |
| Development Tool | Altera MAX+PLUS II (legacy) | β |
| RoHS Status | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS compliance status] |
| Lifecycle Status | Obsolete - last time buy was late 1990s | β |
| Usable Gates | β | 900 (typical) |
| Maximum Frequency | β | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | β | 50 ns |
| Supply Voltage (VCC) | β | 5 V (typical) |
| Dedicated Input Pins | β | 12 |
| Programming Cycles | β | 100 (minimum) |
| Boundary Scan | β | IEEE 1149.1 JTAG (selected speed grades) |