EP910ILC-50 vs EP910ILC-12 Comparison
Detailed side-by-side comparison of EP910ILC-50 by Intel and EP910ILC-12 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910ILC-50 | EP910ILC-12 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.85 | $12.40 |
| Family | Altera Classic EPLD | Altera EP910 Classic EPLD |
| Macrocells | 24 | β |
| Usable Gates | 900 (typical) | 450 (typical) |
| Maximum Frequency | [DATA_NEEDED: fMAX value from datasheet] | β |
| Pin-to-Pin Delay (tpd) | 50 ns | β |
| Supply Voltage (VCC) | 5 V (typical) | 4.75 V to 5.25 V |
| User I/O Pins | 24 | β |
| Dedicated Input Pins | 12 | β |
| Package | PLCC-44 (J-lead) | 28-PLCC (J-Lead, 11.5 x 11.5 mm) |
| Mounting Type | Surface Mount (socket-compatible) | Surface Mount |
| Technology | CMOS EPROM, UV-erasable | β |
| Operating Temperature | 0C to +70C (commercial) | -40 Β°C to +85 Β°C (industrial grade, 'I' suffix) |
| Programming Cycles | 100 (minimum) | β |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Product Type | β | Classic EPLD (Erasable Programmable Logic Device) |
| Number of Macrocells | β | 24 |
| Propagation Delay (tPD) | β | 12 ns (max) |
| Nominal Supply | β | 5 V |
| Memory Technology | β | UV-erasable CMOS EPROM |
| Configuration Storage | β | Non-volatile EPROM (instant-on) |
| Programming Method | β | Altera programming algorithm (serial/parallel master-slave) |
| MSL Level | β | [DATA_NEEDED: MSL level] |
| Number of Pins | β | 28 |
| Feedback Paths | β | 16 dedicated |