EP910ILC-50 vs EP910IPC-50 Comparison
Detailed side-by-side comparison of EP910ILC-50 by Intel and EP910IPC-50 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910IPC-50
EP910IPC-50 - Altera Classic EPLD, 50ns, 24 I/O, DIP-40 | Altera
EP910IPC-50 ObsoleteSpecification Comparison
| Parameter | EP910ILC-50 | EP910IPC-50 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.85 | $13.85 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | β |
| Usable Gates | 900 (typical) | β |
| Maximum Frequency | [DATA_NEEDED: fMAX value from datasheet] | β |
| Pin-to-Pin Delay (tpd) | 50 ns | β |
| Supply Voltage (VCC) | 5 V (typical) | 4.75 V to 5.25 V (5 V nominal) |
| User I/O Pins | 24 | 24 |
| Dedicated Input Pins | 12 | β |
| Package | PLCC-44 (J-lead) | 40-pin Ceramic DIP (IPC, windowed) |
| Mounting Type | Surface Mount (socket-compatible) | Through-Hole (DIP) |
| Technology | CMOS EPROM, UV-erasable | CMOS EPROM cell |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Programming Cycles | 100 (minimum) | β |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not stated in verified data] |
| Product Type | β | Erasable Programmable Logic Device (EPLD) |
| Logic Capacity | β | [DATA_NEEDED: macrocell count / equivalent gates] |
| Propagation Delay (tPD) | β | 50 ns |
| Clock-to-Output (tCO) | β | 35 ns |
| Maximum Toggle Frequency | β | [DATA_NEEDED: fMAX] |
| Programming Method | β | Off-board EPROM programmer + UV erase |
| Erasure Method | β | UV light through ceramic window (IPC package) |