EP910IPC-25 vs EP910IPC-12 Comparison
Detailed side-by-side comparison of EP910IPC-25 by Intel and EP910IPC-12 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-25 | EP910IPC-12 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.40 | $14.20 |
| Family | Classic EPLD (EP910 series) | Classic EPLD |
| Manufacturer | Altera (now Intel) | β |
| Architecture | PAL-type EPLD, CMOS, UV/OTP | β |
| Usable Gates | 450 | 450 |
| Macrocells | 24 | 24 |
| Product Terms | 240 | β |
| Propagation Delay (tPD) | 25 ns | β |
| Maximum Frequency (fMAX) | 40 MHz | β |
| Dedicated Inputs | 12 | 10 |
| Bidirectional I/O Lines | 24 | β |
| Total Inputs (max) | 36 | β |
| Total Outputs (max) | 24 | β |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Operating Temperature | 0C to +70C (commercial grade) | -40C to +85C (industrial) |
| Package | 40-pin PDIP (PDIP-40) | 40-pin PDIP |
| Mounting Type | Through-Hole | Through Hole |
| Programming Method | EPROM cell (OTP / UV erasable) | β |
| Development Tool | MAX+PLUS II | β |
| Maximum Operating Frequency (fMAX) | β | 76.9 MHz |
| Pin-to-Pin Propagation Delay (tPD) | β | 12 ns |
| I/O Pins | β | 24 |
| Technology | β | CMOS EPLD (UV-erasable or OTP) |
| Programming Toolchain | β | MAX+PLUS II |
| Logic Capacity | β | Equivalent to ~24 PAL16V8s |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |