EP910IPC-12 - Classic 24-Macrocell EPLD, 5V, 40-Pin PDIP | Altera
MPN: EP910IPC-12 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $24.95 | $249.50 |
| 100 | $19.75 | $1,975.00 |
| 500 | $16.5 | $8,250.00 |
| 1,000 | $14.2 | $14,200.00 |
EP910IPC-12 Overview
An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the flexibility of a PLD with on-chip macrocell architecture. In the broader hierarchy, the EPLD sits between simple PAL/GAL devices and larger CPLDs/FPGAs - it offers erasable reprogrammability, deterministic timing, and a fixed but flexible macrocell structure suited to medium-complexity logic replacement. The Classic family from Altera was the precursor to the MAX series and introduced 24 macrocells with predictable pin-to-pin delays, making them suitable for synchronous and asynchronous state machines, address decoding, and peripheral control.
Key features of the EP910IPC-12 include 24 macrocells, 10 dedicated input pins, 24 I/O pins, 12 ns pin-to-pin propagation delay (tPD), and a 76.9 MHz internal fMAX for registered logic. The device supports in-system UV-erase (windowed versions) or one-time-programmable (OTP) operation, includes a JTAG-style test mode for functional verification during production, and offers 3.3V/5V mixed-mode I/O via the Altera MAX+PLUS II development environment.
Architecturally, the EP910IPC-12 uses a sum-of-products PLA feed driving a flexible macrocell flip-flop array, with global and per-macrocell clock controls. Each macrocell contains a programmable D/T/J-K flip-flop, output enable polarity, and feedback selection, allowing the device to implement registered, combinatorial, and I/O-buried logic with deterministic 12 ns delays. The 5V VCC and TTL-compatible I/O make the part compatible with legacy 74-series logic and 5V microprocessors.
Typical applications include bus-interface and address-decoding glue logic for 8086/68000-era microprocessor systems, peripheral controllers, custom state machines, board-level timing generators, and legacy replacement of 74LS/74ALS discrete logic. The 40-pin PDIP package simplifies through-hole prototyping and field-repair scenarios.
When designing with the EP910IPC-12, note that the Classic EPLD uses the legacy MAX+PLUS II toolchain (modern Quartus does not directly target this family). For new designs the MAX series (EPM7128, EPM3064) is recommended, but the EP910IPC-12 remains a useful part for sustaining legacy 5V systems.
This page synthesizes distributor availability, parametric drop-in alternatives from the EP910 family, and design notes not found in the original datasheet.
Drop-in alternatives for EP910IPC-12 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910IPC-12 (same form factor and footprint) — differing in Package, Family, Supply Voltage (VCC), Propagation Delay (tPD), Programming Method.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910IPC-25
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →EP910ILC-12
✅ Drop-In✓ In Stock
$12.4 / Unit
View Datasheet →EP910IDC-15
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP910DC-15
✅ Drop-In✓ In Stock
$10.75 / Unit
View Datasheet →EP910DC-30
✅ Drop-In✓ In Stock
$15.6 / Unit
View Datasheet →EP910ILC-25
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP910IPC-12 Maximum Ratings & Electrical Characteristics
| Family | Classic EPLD |
| Macrocells | 24 |
| Usable Gates | 450 |
| Maximum Operating Frequency (fMAX) | 76.9 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 12 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Dedicated Inputs | 10 |
| I/O Pins | 24 |
| Package | 40-pin PDIP |
| Mounting Type | Through Hole |
| Technology | CMOS EPLD (UV-erasable or OTP) |
| Operating Temperature | -40C to +85C (industrial) |
| Programming Toolchain | MAX+PLUS II |
| Logic Capacity | Equivalent to ~24 PAL16V8s |
EP910IPC-12 Pin Configuration
| Pin 1 | I1 — Dedicated input 1 |
| Pin 2 | I2 — Dedicated input 2 |
| Pin 3 | I3 — Dedicated input 3 |
| Pin 4 | I4 — Dedicated input 4 |
| Pin 5 | I5 — Dedicated input 5 |
| Pin 6 | I6 — Dedicated input 6 |
| Pin 7 | I7 — Dedicated input 7 |
| Pin 8 | I8 — Dedicated input 8 |
| Pin 9 | I9 — Dedicated input 9 |
| Pin 10 | I10 — Dedicated input 10 |
| Pin 11 | IO1 — Bidirectional I/O 1 |
| Pin 12 | IO2 — Bidirectional I/O 2 |
| Pin 13 | IO3 — Bidirectional I/O 3 |
| Pin 14 | IO4 — Bidirectional I/O 4 |
| Pin 15 | IO5 — Bidirectional I/O 5 |
| Pin 16 | IO6 — Bidirectional I/O 6 |
| Pin 17 | IO7 — Bidirectional I/O 7 |
| Pin 18 | IO8 — Bidirectional I/O 8 |
| Pin 19 | IO9 — Bidirectional I/O 9 |
| Pin 20 | IO10 — Bidirectional I/O 10 |
| Pin 21 | GND — Ground |
| Pin 22 | IO11 — Bidirectional I/O 11 |
| Pin 23 | IO12 — Bidirectional I/O 12 |
| Pin 24 | IO13 — Bidirectional I/O 13 |
| Pin 25 | IO14 — Bidirectional I/O 14 |
| Pin 26 | IO15 — Bidirectional I/O 15 |
| Pin 27 | IO16 — Bidirectional I/O 16 |
| Pin 28 | IO17 — Bidirectional I/O 17 |
| Pin 29 | IO18 — Bidirectional I/O 18 |
| Pin 30 | IO19 — Bidirectional I/O 19 |
| Pin 31 | IO20 — Bidirectional I/O 20 |
| Pin 32 | IO21 — Bidirectional I/O 21 |
| Pin 33 | IO22 — Bidirectional I/O 22 |
| Pin 34 | IO23 — Bidirectional I/O 23 |
| Pin 35 | IO24 — Bidirectional I/O 24 |
| Pin 36 | TEST — Factory test pin (vendor-specific) |
| Pin 37 | NC — Not connected (per datasheet) |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | VCC — +5V supply |
Typical Applications
EP910IPC-12 is suitable for 6 applications: 8086/68000 Bus Address Decoding, Custom State Machine Controllers, Peripheral Chip-Select Generation, Board-Level Timing and Clock Generation, Legacy 74LS/74ALS Discrete Logic Replacement, Prototype and Educational Logic Design.
8086/68000 Bus Address Decoding
The EP910IPC-12's 24 macrocells and 12 ns deterministic tPD make it ideal for legacy 8086, 8088, 68000, and Z80 microprocessor bus address decoding. Each macrocell can implement a sum-of-products product term covering 8-16 address lines, replacing 4-8 discrete 74LS138/74LS139 decoder chips with a single programmable device. The 12 ns tPD comfortably fits within one 8 MHz bus cycle (125 ns), allowing chip-select generation for memory and peripheral banks without wait-state insertion. The Classic EPLD's predictable timing eliminates the gate-delay variability of discrete TTL, and in-system UV-erase allows last-minute address-map revisions during prototype bring-up.
Recommended
Custom State Machine Controllers
The 24-macrocell Classic EPLD architecture and 76.9 MHz fMAX make the EP910IPC-12 a strong fit for custom state-machine controllers in industrial and instrumentation equipment. Each macrocell contains a programmable D/T/J-K flip-flop with local feedback, allowing the EP910IPC-12 to implement 6-12 state FSMs (Finite State Machines) with one-hot, binary, or Gray encoding. The deterministic 12 ns tPD enables asynchronous state transitions without metastability hazards when combined with external synchronizers. Typical implementations include conveyor controllers, motor step-sequencers, protocol converters, and test-fixture sequencers where 5V TTL logic levels and predictable timing matter.
Recommended
Peripheral Chip-Select Generation
The EP910IPC-12 excels at peripheral chip-select and strobe generation in 5V microcontroller and microprocessor systems. With 24 I/O pins and 10 dedicated inputs, the device can monitor up to 34 address/control signals and generate up to 24 independent chip-select outputs, replacing an entire board of 74LS138/139/688 glue logic. The 12 ns tPD ensures chip-selects settle before the peripheral's setup time, and the 5V TTL-compatible I/O interfaces directly with 8051, 68HC11, Z80, and similar 5V MCUs. Reprogrammability via UV window allows last-minute peripheral-map revisions without PCB rework.
Recommended
Board-Level Timing and Clock Generation
The EP910IPC-12's 76.9 MHz fMAX and macrocell flip-flops make it suitable for board-level timing generators, clock dividers, and pulse-width modulation. Each macrocell flip-flop can be configured as a divide-by-2 stage, and chained macrocells create deep binary counters, programmable baud-rate generators, and watchdog timers. The 5V TTL I/O drives 74LS/74F loads directly without buffering. Industrial controllers, instrumentation front-ends, and legacy communication cards commonly used the EP910IPC-12 to generate non-standard clock rates (e.g., 1.8432 MHz, 2.4576 MHz for UART baud-rate generation) from a system master clock.
Recommended
Legacy 74LS/74ALS Discrete Logic Replacement
The EP910IPC-12 was specifically designed to consolidate 74LS, 74ALS, and 74F discrete gates, muxes, latches, and flip-flops onto a single programmable device. With 450 usable gates, the EP910IPC-12 can replace approximately 24 standard 16-pin SSI/MSI logic packages (e.g., 74LS00, 74LS138, 74LS374), reducing PCB area by 60-80% and improving noise immunity through fewer inter-chip connections. Aerospace, military, and industrial OEMs adopted the Classic EPLD family in the late 1980s and 1990s for board-level miniaturization; sustaining these legacy systems today requires continued EP910IPC-12 supply via Rochester Electronics.
Recommended
Prototype and Educational Logic Design
The EP910IPC-12 in the 40-pin PDIP through-hole package is ideal for breadboard prototyping, university digital-logic laboratories, and educational CPLD tutorials. The DIP footprint allows hand-soldering and IC-socket insertion, eliminating the need for fine-pitch QFP soldering stations. Combined with the MAX+PLUS II student-version toolchain, the EP910IPC-12 has been used in thousands of EE/CE courses to teach programmable logic, sum-of-products minimization, and macrocell architecture. While the MAX II/MAX V family has largely superseded the Classic series for new designs, the EP910IPC-12 remains a teaching staple for understanding historical EPLD architecture.
Recommended
Recommended Products Summary
Engineering reference data for EP910IPC-12 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910IPC-25 | EP910ILC-12 | EP910IDC-15 | EP910DC-15 | EP910DC-30 | EP910ILC-25 |
|---|---|---|---|---|---|---|---|
| Package | 40-pin PDIP | 40-pin PDIP - same | 40-pin PDIP - same | 40-pin PDIP - same | 40-pin PDIP - same | 40-pin PDIP - same | 40-pin PDIP - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tPD) | 12 ns | 25 ns | 12 ns | 15 ns | 15 ns | 30 ns | 25 ns |
| Maximum Frequency (fMAX) | 76.9 MHz | ~40 MHz | 76.9 MHz | ~62.5 MHz | ~62.5 MHz | ~33 MHz | ~40 MHz |
| Supply Voltage | 5V | 5V | 5V | 5V | 5V | 5V | 5V |
| Temperature Grade | Industrial (-40C to +85C) | Industrial | Industrial | Industrial | Commercial | Commercial | Industrial |
| Lifecycle Status | Obsolete (Rochester sustained) | Obsolete (Rochester sustained) | Obsolete (Rochester sustained) | Obsolete (Rochester sustained) | Obsolete (Rochester sustained) | Obsolete (Rochester sustained) | Obsolete (Rochester sustained) |
Key Differentiators
- Fastest speed grade in the EP910 Classic EPLD family (vs EP910IPC-25)
- Drop-in compatible with full EP910 Classic 40-pin PDIP family (vs EP910ILC-12)
- Sustained long-term supply via Rochester Electronics (vs Modern MAX II CPLD (EPM240T100C5N))
Design Notes
Estimated: Do not attempt to program the EP910IPC-12 with modern Quartus software - the Classic EPLD family is supported only by the legacy Altera MAX+PLUS II toolchain (versions 9.x and earlier). MAX+PLUS II runs on Windows XP/2000 era hardware or in DOS-box emulation. Designers migrating from EP910 to MAX II/MAX V must redraw schematics, reassign pins, and regenerate JEDEC files because the macrocell architecture, programming algorithm, and JTAG chain differ significantly. Always verify the JEDEC fuse-map with a second tool (e.g., third-party JEDEC viewers) before committing to ceramic or windowed production units.
The EP910IPC-12 requires a stable 5V +/- 5% supply (4.75V to 5.25V). Decouple VCC (pin 40) with a 0.1 uF ceramic capacitor placed within 5 mm of the package, plus a 10 uF tantalum or aluminum bulk capacitor on the same rail. The Classic EPLD's I/O pins can drive 25 mA per pin (DC sink) and source 4 mA (DC source), so designing for sink-loaded TTL loads (e.g., 74LS inputs) is straightforward; for source-loaded loads (e.g., LED indicators) ensure the 4 mA budget is respected or buffer with an external transistor.
For 40-pin PDIP through-hole designs, route all 24 bidirectional I/O signals on one PCB side and all 10 dedicated inputs on the other, leaving pins 21 (GND), 36 (TEST), 37-39 (NC), and 40 (VCC) as the power/test periphery. Keep signal traces under 50 mm to avoid reflections on the 76.9 MHz fMAX signals. Place a ground plane beneath the IC to provide a low-impedance return path and to reduce EMI from the high-speed macrocell outputs.
Compliance Information
RoHS and lead-free status not explicitly stated in available datasheet extracts; the EP910IPC-12 is an obsolete Altera part sustained by Rochester Electronics. Refer to Rochester Electronics' product documentation for current compliance certifications.
