EP910IPC-25 - 24 Macrocell Classic EPLD 25ns PDIP-40 | Intel
MPN: EP910IPC-25 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.75 | $1,375.00 |
| 500 | $11.9 | $5,950.00 |
| 1,000 | $10.4 | $10,400.00 |
EP910IPC-25 Overview
An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that combines the non-volatile, field-programmable architecture of an EPROM with sum-of-products logic arrays. EPLDs sit in the broader taxonomy as: EPLD -> PLD (Programmable Logic Device) -> programmable logic -> digital IC -> semiconductor. They were widely deployed before modern CPLDs and FPGAs dominated new designs, and they remain valuable for legacy system maintenance, repair, and industrial control applications where pin-compatible replacement of an original Classic EPLD is required.
Key features include 25 ns maximum propagation delay (tPD), 5 V single-supply CMOS operation, 240 product terms, JTAG-compatible in-system verification, and on-board logic test circuitry for AC specification validation during production flow. The EP910 family is supported by the MAX+PLUS II development system, allowing engineers to capture schematics, synthesize logic, and program the device via the Altera programming algorithm.
The EP910IPC-25 uses a PAL-type architecture with a programmable AND/OR array driving 24 macrocell flip-flops. Each macrocell can be configured as D, T, JK, or SR flip-flop with individual product-term clock, reset, and preset control. The 'I' temperature grade designates commercial (0C to 70C) operation, while the 'PC' package suffix denotes the 40-pin plastic DIP. The '25' suffix identifies the speed grade (25 ns tPD). This combination of CMOS low power and TTL-compatible I/O makes the EP910 well-suited for glue-logic replacement in industrial bus interfaces and peripheral controllers.
Typical applications include legacy glue-logic replacement in industrial controllers, address decoding and interrupt steering in 5 V bus systems, peripheral interface state machines, and replacement of discrete 74-series TTL in long-life-cycle equipment. Designers maintaining older Intel 8086/8088 or Motorola 68000 systems often turn to the EP910 family when they need a programmable alternative to a board full of discrete logic.
When designing with the EP910IPC-25, ensure the 5 V supply rail is well-decoupled with 0.1 uF ceramic capacitors near each VCC pin and that all unused I/O pins are tied to a defined logic level. The device is one-time programmable (OTP) via UV window or programmer socket, so the design must be verified in simulation before committing to silicon.
This page synthesizes distributor stock, pricing as of 2026-09-10, pin-compatible drop-in alternatives from the same Classic EPLD family, and practical design notes for engineers maintaining legacy 5 V programmable-logic systems - information not consolidated on the manufacturer product page.
Drop-in alternatives for EP910IPC-25 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910IPC-25 (same form factor and footprint) β differing in Package, Mounting Type, Technology, Programming Method, Operating Temperature.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP910IPC-20
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP910IPC-15
β Drop-Inβ In Stock
$7.95 / Unit
View Datasheet βEP910IPC-12
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$14.2 / Unit
View Datasheet βEP910ILC-25
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$9.95 / Unit
View Datasheet βEP910ILI-25
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$7.25 / Unit
View Datasheet βEP910PC-30
β Drop-Inβ In Stock
$6.5 / Unit
View Datasheet βEP910IPC-25 Maximum Ratings & Electrical Characteristics
| Family | Classic EPLD (EP910 series) |
| Manufacturer | Altera (now Intel) |
| Architecture | PAL-type EPLD, CMOS, UV/OTP |
| Usable Gates | 450 |
| Macrocells | 24 |
| Product Terms | 240 |
| Propagation Delay (tPD) | 25 ns |
| Maximum Frequency (fMAX) | 40 MHz |
| Dedicated Inputs | 12 |
| Bidirectional I/O Lines | 24 |
| Total Inputs (max) | 36 |
| Total Outputs (max) | 24 |
| Supply Voltage (VCC) | 5 V |
| Operating Temperature | 0C to +70C (commercial grade) |
| Package | 40-pin PDIP (PDIP-40) |
| Mounting Type | Through-Hole |
| Programming Method | EPROM cell (OTP / UV erasable) |
| Development Tool | MAX+PLUS II |
EP910IPC-25 Pin Configuration
| Pin 1 | I/O β Bidirectional I/O pin (macrocell 1) |
| Pin 2 | I/O β Bidirectional I/O pin (macrocell 2) |
| Pin 3 | I/O β Bidirectional I/O pin (macrocell 3) |
| Pin 4 | I/O β Bidirectional I/O pin (macrocell 4) |
| Pin 5 | I/O β Bidirectional I/O pin (macrocell 5) |
| Pin 6 | I/O β Bidirectional I/O pin (macrocell 6) |
| Pin 7 | I/O β Bidirectional I/O pin (macrocell 7) |
| Pin 8 | I/O β Bidirectional I/O pin (macrocell 8) |
| Pin 9 | I/O β Bidirectional I/O pin (macrocell 9) |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β Bidirectional I/O pin (macrocell 10) |
| Pin 12 | I/O β Bidirectional I/O pin (macrocell 11) |
| Pin 13 | I/O β Bidirectional I/O pin (macrocell 12) |
| Pin 14 | INPUT β Dedicated input |
| Pin 15 | INPUT β Dedicated input |
| Pin 16 | INPUT β Dedicated input |
| Pin 17 | INPUT β Dedicated input |
| Pin 18 | INPUT β Dedicated input |
| Pin 19 | INPUT β Dedicated input |
| Pin 20 | VCC β +5 V supply |
| Pin 21 | INPUT β Dedicated input |
| Pin 22 | INPUT β Dedicated input |
| Pin 23 | INPUT β Dedicated input |
| Pin 24 | INPUT β Dedicated input |
| Pin 25 | INPUT β Dedicated input |
| Pin 26 | I/O β Bidirectional I/O pin (macrocell 13) |
| Pin 27 | I/O β Bidirectional I/O pin (macrocell 14) |
| Pin 28 | I/O β Bidirectional I/O pin (macrocell 15) |
| Pin 29 | I/O β Bidirectional I/O pin (macrocell 16) |
| Pin 30 | I/O β Bidirectional I/O pin (macrocell 17) |
| Pin 31 | I/O β Bidirectional I/O pin (macrocell 18) |
| Pin 32 | I/O β Bidirectional I/O pin (macrocell 19) |
| Pin 33 | I/O β Bidirectional I/O pin (macrocell 20) |
| Pin 34 | I/O β Bidirectional I/O pin (macrocell 21) |
| Pin 35 | I/O β Bidirectional I/O pin (macrocell 22) |
| Pin 36 | I/O β Bidirectional I/O pin (macrocell 23) |
| Pin 37 | I/O β Bidirectional I/O pin (macrocell 24) |
| Pin 38 | I/O β Bidirectional I/O pin |
| Pin 39 | I/O β Bidirectional I/O pin |
| Pin 40 | I/O β Bidirectional I/O pin |
Typical Applications
EP910IPC-25 is suitable for 6 applications: Legacy Industrial Glue Logic, Address Decoding and Interrupt Steering, Peripheral Interface State Machines, Vintage Computer Restoration, Test and Measurement Equipment, Medical Equipment Long-Life Maintenance.
Legacy Industrial Glue Logic
Replaces multiple 74-series TTL packages on industrial control boards where the original EP910IPC-25 has failed. The EP910's 24 macrocells and 240 product terms consolidate address decoding, bus arbitration, and interrupt steering into a single 5 V device. Its 25 ns tPD is more than adequate for legacy 8-bit and 16-bit microprocessor glue, and the through-hole PDIP-40 footprint allows hand-soldering for repair work. Industrial users value the deterministic propagation delay, which avoids the jitter and configuration-loading latency of modern SRAM-based FPGAs in deterministic control loops.
Recommended
Address Decoding and Interrupt Steering
Decodes memory and I/O address spaces in 8086/8088, Z80, or 68000-based embedded systems where the EP910IPC-25's 12 dedicated inputs and 24 outputs can map the full 16-bit address bus plus control signals. The 24 macrocells are configured as combinational AND/OR arrays producing individual chip-select lines for ROM, RAM, and peripheral devices. With 25 ns tPD the EP910 inserts minimal wait states, and its 5 V CMOS I/O is directly TTL-compatible with the bus transceivers of that era. This application is one of the most common uses of the EP910 family in vintage computing restorations.
Recommended
Peripheral Interface State Machines
Implements serial-to-parallel converters, hand-shake controllers, and DMA sequencers where the EP910IPC-25's 24 macrocell flip-flops provide sufficient state-machine width. Each macrocell supports D, T, JK, or SR flip-flop configuration with product-term clock, reset, and preset, allowing flexible state encoding. The 25 ns tPD delivers up to 40 MHz state-clock frequency, suitable for many UART, GPIB, and IEEE-488 peripheral bridges. The 5 V single-supply operation simplifies power design in mixed analog/digital systems.
Recommended
Vintage Computer Restoration
Recreates lost or damaged logic in vintage computing systems where the original 24-pin or 28-pin PAL/GAL devices cannot be sourced. The EP910IPC-25 is pin-compatible with the original through-hole PDIP-40 footprint and can be programmed with the same JEDEC fuse map as a vintage 74-series replacement. Hobbyists restoring IBM PC, Apple II, or CP/M-era machines turn to the EP910 because its 5 V TTL-compatible I/O matches the original bus signaling and its 25 ns delay is indistinguishable from the discrete logic it replaces. The MAX+PLUS II toolchain, though legacy, is freely available and well-documented.
Recommended
Test and Measurement Equipment
Provides custom stimulus and timing logic in legacy bench instruments such as GPIB controllers, frequency counters, and switch matrices where the EP910IPC-25's deterministic 25 ns delay is critical for measurement accuracy. The OTP EPROM cells ensure configuration stability over the long calibration intervals of industrial test equipment. With 24 bidirectional I/O lines the EP910 can directly drive front-panel switch matrices and indicator LEDs without external buffers. Its 5 V operation is compatible with the analog front ends of legacy instruments.
Recommended
Medical Equipment Long-Life Maintenance
Maintains regulatory-approved medical instruments that were designed around the EP910IPC-25 and require form-fit-function replacement when the original device fails. Because medical equipment undergoes extensive FDA certification that is tied to the exact BOM, any replacement EPLD must be pin-compatible and parametrically equivalent to the original. The EP910IPC-25's 25 ns tPD, 24 macrocells, and 240 product terms are precisely specified in the original Altera datasheet, allowing qualification engineers to validate the replacement without re-certifying the entire system. Rochester Electronics is the typical authorized source for this medical-grade maintenance scenario.
Recommended
Recommended Products Summary
Engineering reference data for EP910IPC-25 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910IPC-20 | EP910IPC-15 | EP910IPC-12 | EP910ILC-25 | EP910ILI-25 | EP910PC-30 |
|---|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | PDIP-40 (through-hole) | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same |
| Propagation Delay (tPD) | 25 ns | 20 ns (faster) | 15 ns (faster) | 12 ns (fastest) | 25 ns (same) | 25 ns (same) | 30 ns (slower) |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Usable Gates | 450 | 450 | 450 | 450 | 450 | 450 | 450 |
| Product Terms | 240 | 240 | 240 | 240 | 240 | 240 | 240 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Temperature Grade | Commercial (0C to +70C) | Commercial | Commercial | Commercial | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Commercial |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Pin-compatible upgrade path within the EP910 family (vs EP910IPC-15)
- Industrial temperature grade option in the same footprint (vs EP910ILC-25)
- Larger macrocell count than EP610 family (vs EP610IPC-25)
Design Notes
The EP910IPC-25 requires a clean 5 V Β±5% supply. Place a 0.1 uF ceramic decoupling capacitor as close as possible to each VCC pin (pin 20 and any other VCC pins per datasheet) and a bulk 10 uF tantalum or aluminum electrolytic at the board-level supply entry. The CMOS core draws modest supply current (~150 mA ICC typical at 25 ns), but the 24 TTL-compatible I/O lines can source/sink significant current during switching, so a low-impedance ground is also important. Do not rely on the EP910's VCC pin alone to provide logic-level reference - keep analog and digital grounds separate if mixed-signal ICs share the board.
Through-hole PDIP-40 layouts require a DIP socket for in-system programming and for ease of replacement during prototyping. Use a high-quality machined-pin socket (e.g., Aries or Mill-Max) rather than a stamped-spring socket for production, especially if the EP910 will be removed and reinserted during board rework. Maintain at least 0.1 inch of clearance around the package for test clip access to all 40 pins. Route all I/O traces on the inner PCB layers or with controlled impedance if any trace exceeds 50 mm in length to avoid transmission-line effects at the 25 ns rise/fall times.
Three pitfalls to avoid when designing with the EP910IPC-25. First, the device is one-time programmable (OTP) - UV-window packages can be erased, but production OTP parts cannot be reprogrammed; always verify the design in MAX+PLUS II simulation before programming. Second, all unused I/O pins MUST be tied to a defined logic level (VCC or GND) - floating inputs can draw excessive supply current and may oscillate, corrupting adjacent logic. Third, the macrocell flip-flop product-term clock must be carefully de-glitched: product terms wider than 4-5 inputs can produce glitches during input transitions, which the EP910's clock network will faithfully propagate to the flip-flop outputs.
The EP910IPC-25's 24 bidirectional I/O lines are TTL-compatible but lack slew-rate control; multiple I/O switching simultaneously can produce significant ground bounce on a poorly designed PCB. Place a ground plane directly beneath the EP910 and use 0.1 uF ceramic bypass on every VCC pin. If the EP910 drives long cables or backplane buses, add 22-33 ohm series-termination resistors at the EP910 outputs to dampen reflections. For designs where multiple EP910 devices share a bus, add small (47-100 ohm) pull-up resistors on shared control lines to suppress noise during power-up before the EP910's internal reset releases.
Compliance Information
The EP910IPC-25 was designed and manufactured before the RoHS directive took effect (2006); original Altera/Intel parts contain lead-bearing solder and are non-compliant with RoHS. RoHS-compliant lead-free variants may have been produced under specific part numbers - confirm with the distributor. Not applicable for AEC-Q100 automotive qualification.
