EP910IPC-25 vs EP910PC-30 Comparison
Detailed side-by-side comparison of EP910IPC-25 by Intel and EP910PC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-25 | EP910PC-30 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.40 | $6.50 |
| Family | Classic EPLD (EP910 series) | Altera Classic EPLD |
| Manufacturer | Altera (now Intel) | β |
| Architecture | PAL-type EPLD, CMOS, UV/OTP | β |
| Usable Gates | 450 | ~450 |
| Macrocells | 24 | 24 |
| Product Terms | 240 | β |
| Propagation Delay (tPD) | 25 ns | β |
| Maximum Frequency (fMAX) | 40 MHz | β |
| Dedicated Inputs | 12 | β |
| Bidirectional I/O Lines | 24 | β |
| Total Inputs (max) | 36 | β |
| Total Outputs (max) | 24 | β |
| Supply Voltage (VCC) | 5 V | 5 V Β±10% |
| Operating Temperature | 0C to +70C (commercial grade) | 0C to +70C (commercial) |
| Package | 40-pin PDIP (PDIP-40) | PDIP-40 (plastic DIP, 0.6 inch) |
| Mounting Type | Through-Hole | Through-hole DIP |
| Programming Method | EPROM cell (OTP / UV erasable) | β |
| Development Tool | MAX+PLUS II | β |
| Pin-to-Pin Propagation Delay (tPD) | β | 30 ns |
| Maximum Counter Frequency (fCNT) | β | 33.3 MHz |
| Logic Inputs | β | 36 dedicated |
| I/O Pins | β | 12 bidirectional |
| Logic Array Blocks (LABs) | β | 4 |
| Programming Technology | β | UV-erasable EPROM cell |
| TTL Emulation | β | 100% TTL-compatible |
| Power Dissipation | β | [DATA_NEEDED: power dissipation mW] |
| RoHS Status | β | Non-compliant (contains lead, PDIP package) |