EP910IPC-50 vs EP910ILC-50 Comparison
Detailed side-by-side comparison of EP910IPC-50 by Altera and EP910ILC-50 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-50 | EP910ILC-50 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $13.85 | $10.85 |
| Product Type | Erasable Programmable Logic Device (EPLD) | β |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Logic Capacity | [DATA_NEEDED: macrocell count / equivalent gates] | β |
| Propagation Delay (tPD) | 50 ns | β |
| Clock-to-Output (tCO) | 35 ns | β |
| Maximum Toggle Frequency | [DATA_NEEDED: fMAX] | β |
| User I/O Pins | 24 | 24 |
| Package | 40-pin Ceramic DIP (IPC, windowed) | PLCC-44 (J-lead) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (typical) |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Technology | CMOS EPROM cell | CMOS EPROM, UV-erasable |
| Programming Method | Off-board EPROM programmer + UV erase | β |
| Erasure Method | UV light through ceramic window (IPC package) | β |
| Mounting Type | Through-Hole (DIP) | Surface Mount (socket-compatible) |
| RoHS Status | [DATA_NEEDED: not stated in verified data] | [DATA_NEEDED: RoHS compliance status] |
| Macrocells | β | 24 |
| Usable Gates | β | 900 (typical) |
| Maximum Frequency | β | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | β | 50 ns |
| Dedicated Input Pins | β | 12 |
| Programming Cycles | β | 100 (minimum) |
| Boundary Scan | β | IEEE 1149.1 JTAG (selected speed grades) |