EP910LC-32 vs EP910LC-35 Comparison

Detailed side-by-side comparison of EP910LC-32 by Altera and EP910LC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP910LC-32

EP910LC-32 - 24-Macrocell Classic EPLD, PLCC-32 | Altera

EP910LC-32 Obsolete
Altera
EP910LC-35

EP910LC-35 - 24 Macrocell Classic EPLD, 35ns | Intel/Altera

EP910LC-35 Obsolete

Specification Comparison

Parameter EP910LC-32 EP910LC-35
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.85 $18.75
Device Family Altera Classic EPLD β€”
Number of Macrocells 24 β€”
Number of Usable Gates 900 gates (typical) β€”
Number of Dedicated Inputs 10 β€”
Number of I/O Pins 20 β€”
Package PLCC-32 PLCC-44 (J-lead, LC suffix)
Speed Grade -32 β€”
Maximum Toggle Frequency (fMAX) [DATA_NEEDED: fMAX value in MHz for -32 grade] β€”
Pin-to-Pin Propagation Delay (tPD) [DATA_NEEDED: tPD in ns for -32 grade] β€”
Supply Voltage (VCC) 5 V 5 V
Logic Family Low-power CMOS (LC suffix) β€”
Programming Method UV-erasable or one-time programmable (OTP for LC windowless variant) β€”
Operating Temperature Range [DATA_NEEDED: commercial or industrial grade] β€”
I/O Standard TTL-compatible β€”
Mounting Type Surface Mount (PLCC socket or direct solder) β€”
RoHS Status unknown Not applicable (legacy product)
MSL Level unknown β€”
Product Type β€” EPLD (Erasable Programmable Logic Device)
Family β€” Classic (EP910)
Macrocells β€” 24
Usable Gates β€” 450
Propagation Delay (tPD) β€” 35 ns
Maximum Toggle Frequency β€” 28.6 MHz
Technology β€” CMOS EPROM
Operating Temperature β€” 0C to +70C (commercial)
Pin Count β€” 44
Programmable Flip-Flops β€” Yes (per macrocell)
Output Enable Control β€” Per macrocell
Erasure Method β€” UV (windowed) or OTP (plastic)

Datasheets & Resources

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