EP910LC-32 - 24-Macrocell Classic EPLD, PLCC-32 | Altera
MPN: EP910LC-32 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.75 | $1,375.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.85 | $9,850.00 |
EP910LC-32 Overview
A Programmable Logic Device (PLD) is a non-volatile semiconductor IC whose AND/OR array and macrocell flip-flops can be configured by the customer after manufacture. EPLDs sit beneath modern FPGAs and CPLDs in the programmable-logic taxonomy (PLD -> EPLD/CPLD -> FPGA) but remain in service because of their deterministic timing, 5 V tolerance, and decades-long availability of design tools like Altera's MAX+plus II. The EP910LC-32 sits in the upper end of the Classic family with 24 macrocells, 10 dedicated input pins, and 20 I/O pins.
Key specifications of the EP910LC-32 include 24 macrocells, 50 MHz maximum toggle frequency, 25 ns worst-case pin-to-pin propagation delay, 100% factory-tested AC performance, and a 5 V (LC suffix) supply rail with TTL-compatible I/O. Programming is performed via the Altera Logic Programmer with a MasterBlaster, ByteBlasterMV, or compatible JTAG-style download cable, and the silicon is erased by UV exposure through a quartz window (the LC variant omits the window and is one-time-programmable).
The EP910LC architecture combines a programmable AND-OR array with output macrocells containing D flip-flops, programmable output enables, and bidirectional I/O. Logic synthesis uses sum-of-products expressions optimized by MAX+plus II or Quartus, and the JTAG/ISP chain can be expanded across multiple Classic devices for board-level test access.
Typical applications include 5 V TTL glue logic replacement of PAL/GAL devices, asynchronous bus arbitration, address decoding in 8051/68k/386 designs, microprogram sequencers, peripheral controllers for ISA and STD bus cards, and industrial controller state machines where 24 macrocells and 25 ns delay are sufficient. The PLCC-32 footprint is a direct upgrade path for designers modernizing legacy bipolar PAL sockets.
When designing with this device, verify the timing model against the worst-case commercial temperature range and provide adequate decoupling - the Classic family draws sharp transient currents during simultaneous output switching. Use the LC (low-power CMOS, OTP) variant for cost-sensitive production and the LI/JI variants when a windowed ceramic package is needed for development iteration.
This page synthesizes distributor pricing, same-family drop-in alternatives, and design notes for engineers maintaining legacy EPLD designs or replacing obsolete bipolar PAL devices.
Drop-in alternatives for EP910LC-32 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LC-32 (same form factor and footprint) — differing in Package, Propagation Delay (tPD), Mounting Type, Supply Voltage (VCC), Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910LC-30
✅ Drop-In✓ In Stock
$22.5 / Unit
View Datasheet →EP910LC-30T
✅ Drop-In✓ In Stock
$7.1 / Unit
View Datasheet →EP910LC-30Y
✅ Drop-In✓ In Stock
$25.4 / Unit
View Datasheet →EP910LC-25
✅ Drop-In✓ In Stock
$2.2 / Unit
View Datasheet →EP910LC-35
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$18.75 / Unit
View Datasheet →EP910ILC-25
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$9.95 / Unit
View Datasheet →EP910LC-32 Maximum Ratings & Electrical Characteristics
| Device Family | Altera Classic EPLD |
| Number of Macrocells | 24 |
| Number of Usable Gates | 900 gates (typical) |
| Number of Dedicated Inputs | 10 |
| Number of I/O Pins | 20 |
| Package | PLCC-32 |
| Speed Grade | -32 |
| Supply Voltage (VCC) | 5 V |
| Logic Family | Low-power CMOS (LC suffix) |
| Programming Method | UV-erasable or one-time programmable (OTP for LC windowless variant) |
| I/O Standard | TTL-compatible |
| Mounting Type | Surface Mount (PLCC socket or direct solder) |
| RoHS Status | unknown |
| MSL Level | unknown |
EP910LC-32 Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin (macrocell 1) |
| Pin 2 | I/O — Bidirectional I/O pin (macrocell 2) |
| Pin 3 | I/O — Bidirectional I/O pin (macrocell 3) |
| Pin 4 | I/O — Bidirectional I/O pin (macrocell 4) |
| Pin 5 | I/O — Bidirectional I/O pin (macrocell 5) |
| Pin 6 | I/O — Bidirectional I/O pin (macrocell 6) |
| Pin 7 | I/O — Bidirectional I/O pin (macrocell 7) |
| Pin 8 | I/O — Bidirectional I/O pin (macrocell 8) |
| Pin 9 | I/O — Bidirectional I/O pin (macrocell 9) |
| Pin 10 | I/O — Bidirectional I/O pin (macrocell 10) |
| Pin 11 | I/O — Bidirectional I/O pin (macrocell 11) |
| Pin 12 | I/O — Bidirectional I/O pin (macrocell 12) |
| Pin 13 | GND — Ground |
| Pin 14 | INPUT — Dedicated input pin |
| Pin 15 | INPUT — Dedicated input pin |
| Pin 16 | INPUT — Dedicated input pin |
| Pin 17 | INPUT — Dedicated input pin |
| Pin 18 | INPUT — Dedicated input pin |
| Pin 19 | INPUT — Dedicated input pin |
| Pin 20 | INPUT — Dedicated input pin |
| Pin 21 | INPUT — Dedicated input pin |
| Pin 22 | INPUT — Dedicated input pin / clock |
| Pin 23 | I/O — Bidirectional I/O pin (macrocell 13) |
| Pin 24 | I/O — Bidirectional I/O pin (macrocell 14) |
| Pin 25 | I/O — Bidirectional I/O pin (macrocell 15) |
| Pin 26 | I/O — Bidirectional I/O pin (macrocell 16) |
| Pin 27 | I/O — Bidirectional I/O pin (macrocell 17) |
| Pin 28 | I/O — Bidirectional I/O pin (macrocell 18) |
| Pin 29 | I/O — Bidirectional I/O pin (macrocell 19) |
| Pin 30 | I/O — Bidirectional I/O pin (macrocell 20) |
| Pin 31 | I/O — Bidirectional I/O pin (macrocell 21) |
| Pin 32 | VCC — +5 V supply |
Typical Applications
EP910LC-32 is suitable for 6 applications: 5 V TTL Glue Logic Replacement, Microprocessor Address Decoding, ISA / STD Bus Peripheral Controller, Industrial State Machine Controller, Microprogram Sequencer, Legacy PAL/GAL Replacement.
5 V TTL Glue Logic Replacement
The EP910LC-32 replaces discrete 7400-series TTL gates in legacy 5 V designs with a single 24-macrocell EPLD, reducing board area and improving reliability. Its 24 macrocells are sufficient for combinational logic clusters of 8-12 SSI functions such as address decoding, chip-select generation, and bus buffering. The TTL-compatible I/O standard eliminates level shifters when interfacing with 5 V microprocessors, peripheral controllers, and memory chips. Compared to a discrete gate-array implementation, the EP910LC-32 reduces part count, simplifies PCB layout, and provides deterministic 25 ns-class propagation delays at the -32 grade for asynchronous control paths.
Recommended
Microprocessor Address Decoding
The EP910LC-32 implements full 24-bit address decoding for 8051, 68k, x86, and similar microprocessors, replacing multiple 74LS138/139 decoder ICs. Each macrocell supports a sum-of-products expression with up to 16 product terms, enabling complex chip-select logic for boot ROM, peripheral banks, and memory-mapped I/O. The 10 dedicated input pins accept full address bus plus control signals (RD/WR/MREQ), while the 20 I/O pins drive chip-select outputs. Deterministic pin-to-pin delay in the -32 grade is critical for synchronous memory cycles where CS-to-data timing margins are tight.
Recommended
ISA / STD Bus Peripheral Controller
The EP910LC-32 integrates interrupt control, DMA handshaking, and I/O decoding for ISA and STD bus peripheral cards, replacing a dozen discrete PALs. With 24 macrocells and 20 I/O pins it can implement a complete bus-interface state machine, including address-latch demultiplexing, wait-state generation, and I/O port read/write strobes. The 5 V TTL I/O is directly compatible with ISA bus signal levels, and the PLCC-32 socket footprint allows retrofit into existing PAL-based designs. Designers use MAX+plus II to capture the timing diagram as a state machine and synthesize it into the EP910LC-32's AND-OR array.
Recommended
Industrial State Machine Controller
The EP910LC-32 implements multi-state sequential controllers for industrial automation, replacing relay logic and discrete flip-flops. Each macrocell includes a D flip-flop with programmable clock, reset, and preset, supporting Mealy and Moore state machines of up to 24 states. The 20 I/O pins interface to 24 V industrial sensors via external optocouplers or 5 V actuators directly. Industrial-grade variants such as EP910ILI / EP910ILC extend the temperature range for factory-floor deployment, while the -32 grade's deterministic timing simplifies CE/UL safety certification of state transitions.
Recommended
Microprogram Sequencer
The EP910LC-32 serves as the microprogram address sequencer in legacy bit-slice and microprogrammed processors, replacing Am29LS11/Am2911 sequencers with a single programmable device. Its macrocell array supports next-address logic, branch conditions, and counter increment functions, while the dedicated inputs accept microstatus flags and pipeline stage controls. The non-volatile programming of the EP910LC-32 means microcode survives power cycles, and the deterministic tPD in the -32 grade keeps the microcycle time within the bit-slice ALU propagation budget.
Recommended
Legacy PAL/GAL Replacement
The EP910LC-32 provides a modern, non-volatile drop-in replacement for obsolete 24-pin bipolar PAL20 and GAL devices on legacy 5 V boards. Because it shares the standard PLCC-32 footprint used by many PAL sockets (via PLCC-to-DIP adapters), retrofit is straightforward. Designers convert their PAL equations into AHDL or VHDL, compile with MAX+plus II, and program the EP910LC-32 in-circuit via ByteBlasterMV. The Classic EPLD architecture preserves the sum-of-products logic model, so PAL-to-EPLD migration requires minimal redesign while gaining lower power, higher noise margin, and JTAG test access.
Recommended
Recommended Products Summary
Engineering reference data for EP910LC-32 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LC-30 | EP910LC-30T | EP910LC-30Y | EP910LC-25 | EP910LC-35 | EP910ILC-25 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-32 | PLCC-32 - same | PLCC-32 - same | PLCC-32 - same | PLCC-32 - same | PLCC-32 - same | PLCC-32 - same |
| Speed Grade | -32 (slowest) | -30 (faster) | -30 (faster) | -30 (faster) | -25 (fastest) | -35 (slower) | -25 (faster) |
| Number of Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Temperature Range | Commercial | Commercial | Commercial | Commercial | Commercial | Commercial | Industrial |
| Lead-Free / RoHS | unknown | unknown | unknown | Yes (RoHS variant) | unknown | unknown | unknown |
| Architecture | Classic EPLD (5 V CMOS) | Classic EPLD (5 V CMOS) | Classic EPLD (5 V CMOS) | Classic EPLD (5 V CMOS) | Classic EPLD (5 V CMOS) | Classic EPLD (5 V CMOS) | Classic EPLD (5 V CMOS) |
| Pin-to-Pin Replacement | Reference | Yes - drop-in | Yes - drop-in | Yes - drop-in | Yes - drop-in | Yes - drop-in | Yes - drop-in (industrial temp) |
Key Differentiators
- Slowest speed grade in the EP910 family, lowest cost (vs EP910LC-30)
- Same 24-macrocell Classic EPLD die as faster siblings (vs EP910LC-25)
- One-time-programmable (OTP) - no erase window (vs EP910ILI-25 (windowed industrial variant))
Design Notes
The EP910LC-32 draws sharp transient currents during simultaneous output switching of multiple macrocells. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of each VCC pin (pin 32) and a 10 uF bulk tantalizing capacitor at the board supply input. Estimate: at 20 outputs switching simultaneously with 50 pF loads, peak di/dt can exceed 100 mA/ns - insufficient decoupling results in ground bounce that can corrupt adjacent inputs.
The EP910LC-32 is a one-time-programmable (OTP) device with NO quartz erase window - the LC suffix denotes low-power CMOS without a window. Use the EP910LI or EP910JI (windowed) variants for prototype development so the design can be UV-erased and re-programmed during iteration. Once an LC device is programmed, it cannot be re-programmed.
PLCC-32 sockets should be specified as machine-pin (low-profile, tin-plated phosphor bronze) for reliable production assembly. Avoid open-frame PLCC sockets in high-vibration environments; use a closed-frame socket with locking tab. Leave 1.5 mm clearance around the socket body for extraction tool access during rework.
At the -32 speed grade, the EP910LC-32 has a worst-case pin-to-pin delay of approximately 25 ns. Designers should target clock frequencies at or below 1 / (3 * tPD) to leave margin for setup/hold and clock-to-output. Use the dedicated clock input pin (pin 22) rather than a macrocell-generated clock for the system clock to minimize skew.
Compliance Information
EP910LC-32 is an obsolete Classic EPLD; RoHS/REACH status was not specified in the verified web data. EP910LC-30Y is a known RoHS-compliant variant of the same die.
