EP910LC-35H vs EP910DC-30 Comparison
Detailed side-by-side comparison of EP910LC-35H by Altera and EP910DC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-35H | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $25.00 | $15.60 |
| Family | Classic EPLD (EP910) | Classic EPLD (EP910 series) |
| Logic Elements | 24 macrocells | β |
| Equivalent Gates | 450 usable gates | β |
| Propagation Delay (tpd) | 35 ns | β |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | β |
| Technology | CMOS, UV-erasable EPROM | β |
| Package | 40-pin Ceramic DIP (H suffix) | DIP-40 (through-hole, 600 mil) |
| User I/O Pins | 36 | β |
| Dedicated Inputs | 10 | 36 |
| Operating Temperature | [DATA_NEEDED: operating temperature range grade] | 0C to +70C (commercial) |
| Erasure Method | UV (quartz window on H package) | β |
| Programming Method | Altera hardware programmer | UV-Erasable / OTP |
| Logic Levels | TTL compatible | β |
| Quiescent Current | [DATA_NEEDED: typical ICC value] | β |
| Process Node | [DATA_NEEDED: process geometry] | β |
| Mounting Type | Through-hole (Ceramic DIP) | Through-Hole |
| RoHS Status | unknown | β |
| Lifecycle | Obsolete (long-term supply via Rochester Electronics) | β |
| Architecture | β | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | β | 900 usable gates |
| Macrocells | β | 24 |
| Propagation Delay (tPD) | β | 30 ns (max) |
| Clock Frequency (fCNT) | β | 33.3 MHz |
| Outputs (Macrocells) | β | 24 |
| External Clock Pins | β | 2 (CLK1, CLK2) |
| Supply Voltage | β | 5 V |
| Process Technology | β | CMOS |