EP910LC-35H vs EP910LC-40H Comparison

Detailed side-by-side comparison of EP910LC-35H by Altera and EP910LC-40H by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910LC-35H EP910LC-40H
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $25.00 $9.95
Family Classic EPLD (EP910) Classic EPLD (EP910)
Logic Elements 24 macrocells 24 macro cells / expandable to 48 via expander terms
Equivalent Gates 450 usable gates β€”
Propagation Delay (tpd) 35 ns β€”
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 4.75 V to 5.25 V (5 V nominal)
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable EPROM
Package 40-pin Ceramic DIP (H suffix) 40-pin Ceramic DIP (CDIP-40), JEDEC standard
User I/O Pins 36 β€”
Dedicated Inputs 10 β€”
Operating Temperature [DATA_NEEDED: operating temperature range grade] -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade]
Erasure Method UV (quartz window on H package) β€”
Programming Method Altera hardware programmer UV-erase + EPROM program, ~100 erase cycles
Logic Levels TTL compatible β€”
Quiescent Current [DATA_NEEDED: typical ICC value] β€”
Process Node [DATA_NEEDED: process geometry] β€”
Mounting Type Through-hole (Ceramic DIP) Through-Hole (THT)
RoHS Status unknown [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP]
Lifecycle Obsolete (long-term supply via Rochester Electronics) β€”
Macro Cells β€” 24
Usable Gates β€” 450
Propagation Delay (tPD) β€” 40 ns max
Supply Current (ICC) β€” Low-power CMOS, typical ICC < 100 mA
Speed Grade β€” -40 (40 ns tPD)
I/O Pins β€” [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical]

Datasheets & Resources

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