EP910LC-40H - 40ns Classic EPLD, 24 Macro Cells | Altera
MPN: EP910LC-40H ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $9.95 | $9,950.00 |
EP910LC-40H Overview
What is a Classic EPLD? An EPLD is an Erasable Programmable Logic Device, a category that sits between simple PAL/GAL devices and modern CPLDs/FPGAs in the programmable logic taxonomy. EPLDs are non-volatile, contain a fixed AND/OR logic array with user-programmable interconnect, and were widely used in the 1980s and 1990s for glue logic, address decoding, state machines, and bus interface functions. The Classic family was Altera's flagship EPLD line before being superseded by MAX series CPLDs. Understanding this lineage helps engineers recognize the EP910 as an early-era programmable logic building block rather than a contemporary FPGA.
Key features of the EP910LC-40H include 24 macro cells, 450 system gates, 40 ns pin-to-pin propagation delay (tPD), 5 V single-supply operation (VCC = 4.75 V to 5.25 V), low-power CMOS technology with typical ICC below 100 mA, and UV-erasable EPROM-based configuration. The device is packaged in a 40-pin ceramic DIP (JEDEC CDIP-40) suitable for prototyping, military, and high-reliability applications through-hole assembly. The "LC" (low-power, low-cost) variants consume less current than the original EP910, making them suitable for portable or power-sensitive systems.
Typical applications include address decoding for microprocessor systems, bus arbitration glue logic, state machines and sequencers, peripheral interface controllers (e.g., custom UART, parallel I/O), and replacement of discrete TTL/CMOS logic in legacy industrial, military, and aerospace systems. The Classic EPLD architecture is well-suited to wide combinational decoding and registered logic functions, replacing multiple 74LS/74HC packages with a single programmable device.
When designing with this part, engineers should note that it is a UV-erasable device requiring a quartz-windowed package for erasure, with an endurance of approximately 100 erase/program cycles. Modern design flows use the MAX+PLUS II or Quartus II Classic device support, or migrate new designs to MAX II/MAX V CPLDs with pin-compatible footprints. This page synthesizes distributor pricing, drop-in alternatives, and practical sourcing notes not found in the standalone manufacturer datasheet.
Drop-in alternatives for EP910LC-40H — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LC-40H (same form factor and footprint) — differing in Package, Mounting Type, Supply Voltage (VCC), Technology, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910LC-40
✅ Drop-In✓ In Stock
$52 / Unit
View Datasheet →EP910DC-40
✅ Drop-In✓ In Stock
$13.95 / Unit
View Datasheet →EP910LC-35H
✅ Drop-In✓ In Stock
$25 / Unit
View Datasheet →EP910LC-35
✅ Drop-In✓ In Stock
$18.75 / Unit
View Datasheet →EP910ILC-50
✅ Drop-In✓ In Stock
$10.85 / Unit
View Datasheet →EP910ILC-25
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP910LC-40H Maximum Ratings & Electrical Characteristics
| Family | Classic EPLD (EP910) |
| Macro Cells | 24 |
| Usable Gates | 450 |
| Logic Elements | 24 macro cells / expandable to 48 via expander terms |
| Propagation Delay (tPD) | 40 ns max |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Supply Current (ICC) | Low-power CMOS, typical ICC < 100 mA |
| Technology | CMOS, UV-erasable EPROM |
| Package | 40-pin Ceramic DIP (CDIP-40), JEDEC standard |
| Mounting Type | Through-Hole (THT) |
| Speed Grade | -40 (40 ns tPD) |
| Programming Method | UV-erase + EPROM program, ~100 erase cycles |
EP910LC-40H Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 2 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 3 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 4 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 5 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 6 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 7 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 8 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 9 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 10 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 13 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 14 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 15 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 16 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 17 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 18 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 19 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 20 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 21 | IN0 — Dedicated input pin 0 |
| Pin 22 | IN1 — Dedicated input pin 1 |
| Pin 23 | IN2 — Dedicated input pin 2 |
| Pin 24 | IN3 — Dedicated input pin 3 |
| Pin 25 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 26 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 27 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 28 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 29 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 30 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 31 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 32 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 33 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 34 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 35 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 36 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 37 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 38 | I/O — Bidirectional I/O pin (macro cell) |
| Pin 39 | TMS — JTAG test mode select |
| Pin 40 | VCC — +5 V supply voltage |
Typical Applications
EP910LC-40H is suitable for 6 applications: Microprocessor Address Decoding, Bus Interface Glue Logic, State Machine and Sequencer, Legacy Industrial Control, Military and Aerospace Sustainment, TTL/CMOS Logic Replacement.
Microprocessor Address Decoding
The EP910LC-40H is well-suited to microprocessor address decoding because its 24 macro cells and 450-gate capacity can replace 4-10 standard 74LS138/74HC138 decoder packages. With 40 ns propagation delay, it comfortably decodes 8-16 bit address buses for MPUs running up to 8 MHz (e.g., 8086, 68000 era processors). Its 5 V CMOS technology matches TTL logic levels directly. Wide combinational decoding paths benefit from the EP910's AND/OR logic array, and registered outputs can latch chip-select signals. Compared to discrete logic, a single EP910LC-40H reduces PCB area and improves noise margin.
Recommended
Bus Interface Glue Logic
The EP910LC-40H excels as bus interface glue logic for legacy ISA, STD, and VME bus systems, where it can implement wait-state generators, bus arbiters, and interrupt controllers. The 5 V supply and TTL-compatible I/O match 1980s-1990s bus standards directly. With 36 user I/O pins in the CDIP-40 package, the device offers sufficient pin count for typical bus-side glue logic functions. The 40 ns propagation delay is acceptable for 8-10 MHz bus clocks. UV-erasable EPROM-based configuration allows last-minute design changes during prototype bring-up without re-spinning the PCB.
Recommended
State Machine and Sequencer
State machines and sequencers benefit from the EP910LC-40H's registered macro cells, which provide D flip-flops with feedback for implementing Moore and Mealy state machines of 16-32 states. With 24 macro cells and 40 ns delay, the device implements complex sequencing logic that would otherwise require multiple PAL/GAL devices or dozens of 74LS/74HC packages. The Classic EPLD architecture supports both sum-of-products and registered outputs in the same macro cell, simplifying state-machine design. Programming via MAX+PLUS II with schematic or AHDL entry accelerates design entry for sequential control functions.
Recommended
Legacy Industrial Control
The EP910LC-40H finds continued use in legacy industrial control systems where long-term sustainment requires functional replacement of obsolete or damaged programmable logic. Industrial PLC I/O modules, motor controllers, and process instrumentation originally designed with Classic EPLDs in the 1990s often require identical replacements for field service. The 40-pin ceramic DIP package is well-suited to through-hole industrial PCBs, and the -40C to +85C operating range covers most industrial environments. Rochester Electronics and franchised brokers stock authentic Altera parts for these long-lifecycle applications.
Recommended
Military and Aerospace Sustainment
The EP910LC-40H ceramic "H" variant is qualified for military and aerospace sustainment programs where the ceramic hermetic package (CDIP-40) meets MIL-STD-883 environmental screening requirements. Programs such as avionics upgrades, radar systems, and military communication equipment originally designed with Classic EPLDs require identical replacement parts to avoid re-qualification costs. The -40C to +85C industrial temperature range or extended military temperature grade (in the EP910DC variant) supports harsh-environment operation. Long-term defense contracts benefit from Rochester Electronics' franchised legacy inventory.
Recommended
TTL/CMOS Logic Replacement
The EP910LC-40H replaces clusters of 74LS, 74S, 74F, and 74HC discrete logic packages, reducing PCB area, power consumption, and assembly cost. A single 24-macro-cell EPLD can replace 8-12 SSI/MSI logic packages such as 74LS151 multiplexers, 74LS153 dual 4:1 muxes, 74LS283 adders, and 74LS373 latches. The 5 V CMOS technology draws less current per gate than equivalent 74LS TTL, and the EP910LC low-power variant further reduces quiescent current. Re-designable UV-erasable EPROM configuration enables late-stage design changes that discrete logic cannot accommodate.
Recommended
Recommended Products Summary
Engineering reference data for EP910LC-40H — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LC-40 | EP910DC-40 | EP910LC-35H | EP910ILC-25 |
|---|---|---|---|---|---|
| Package | CDIP-40 (ceramic DIP) | PDIP-40 (plastic DIP) - same footprint | CDIP-40 (ceramic) - same | CDIP-40 (ceramic) - same | CDIP-40 (ceramic) - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Propagation Delay (tPD) | 40 ns | 40 ns | 40 ns | 35 ns (12.5% faster) | 25 ns (37.5% faster) |
| Macro Cells | 24 | 24 | 24 | 24 | 24 |
| Supply Voltage | 5 V (4.75-5.25 V) | 5 V | 5 V | 5 V | 5 V |
| Temperature Grade | Industrial (-40C to +85C) | Industrial | Military (-55C to +125C) | Industrial | Industrial |
| Package Material | Ceramic (hermetic) | Plastic (PDIP) | Ceramic | Ceramic | Ceramic |
| Price (qty 100) | $13.95 (as of 2026-09-10) | $10-12 typical (plastic, lower cost) | $20-30 typical (military screened) | $15-18 typical (faster grade) | $16-22 typical (faster grade) |
Key Differentiators
- Ceramic hermetic package for harsh environments (vs EP910LC-40 (plastic PDIP))
- Lower cost than military-grade EP910DC-40 (vs EP910DC-40 (military temperature))
- 40 ns speed grade optimized for low cost (vs EP910LC-35H (35 ns))
Design Notes
The 40-pin ceramic DIP footprint follows JEDEC standard 0.6 inch row spacing with 2.54 mm (100 mil) pin pitch. Maintain at least 0.5 inch clearance around the UV erasure window for proper lamp alignment during programming. Decoupling: place a 0.1 uF ceramic capacitor between VCC (pin 40) and GND (pin 11) within 0.25 inch of the package, plus a 10 uF tantalum bulk capacitor on the VCC rail. The ceramic DIP package has lower thermal resistance than plastic PDIP, but still requires thermal relief on ground pours. Estimated: power dissipation at 5 V, 24 macro cells switching at 25 MHz is approximately 250 mW; no heatsink required.
The EP910LC-40H is a UV-erasable EPROM device - it CANNOT be re-programmed in-circuit. Erasure requires 30-45 minutes of UV exposure through the quartz window. Programming is performed in a dedicated EPROM programmer (e.g., Data I/O, BP Microsystems) using the MAX+PLUS II Classic device support. End-of-life design: if your application requires in-field reprogramming, migrate to MAX II/MAX V CPLDs which support JTAG ISP. Also note the device is NOT 5 V tolerant of inputs above VCC+0.5 V - tie unused inputs to GND through 10 kohm resistors to prevent latch-up.
The 40 ns propagation delay translates to a maximum toggle frequency of approximately 25 MHz for registered outputs. For combinational paths used in address decoding, ensure setup time at the destination register is met with adequate margin. Add 5-10 ns timing margin for PCB trace delay, signal integrity reflections, and clock skew. Use series termination (22-33 ohms) on clock and high-speed output signals driving >2 inch traces. The Classic EPLD output drive is approximately 4 mA IOL/IOH - sufficient for TTL loads but marginal for high-capacitance buses.
Compliance Information
Ceramic DIP package with lead-bearing terminations - not RoHS compliant. Part is obsolete and out of active production; compliance documentation not maintained by Altera/Intel for the Classic EPLD family. AEC-Q100 not applicable for legacy EPLD product category. REACH and conflict minerals status unknown for obsolete part.
