EP910LC-40H vs EP910ILC-25 Comparison
Detailed side-by-side comparison of EP910LC-40H by Altera and EP910ILC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-40H | EP910ILC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $9.95 |
| Family | Classic EPLD (EP910) | EP910 Classic EPLD |
| Macro Cells | 24 | β |
| Usable Gates | 450 | β |
| Logic Elements | 24 macro cells / expandable to 48 via expander terms | β |
| Propagation Delay (tPD) | 40 ns max | 25 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | β |
| Supply Current (ICC) | Low-power CMOS, typical ICC < 100 mA | β |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM (UV-erasable) |
| Package | 40-pin Ceramic DIP (CDIP-40), JEDEC standard | 44-pin JLCC (windowed ceramic) |
| Mounting Type | Through-Hole (THT) | Surface Mount |
| Operating Temperature | -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] | -40C to +85C (industrial) |
| Speed Grade | -40 (40 ns tPD) | β |
| Programming Method | UV-erase + EPROM program, ~100 erase cycles | β |
| I/O Pins | [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] | β |
| RoHS Status | [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] | non_compliant (ceramic windowed package) |
| Macrocells | β | 24 |
| User I/O Pins | β | 36 |
| Internal Frequency (fMAX) | β | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | β | Sum-of-products AND/OR array |
| Configuration Memory | β | Non-volatile EPROM (windowed ceramic) |
| Supply Voltage | β | 5 V |
| Development Tool | β | Altera MAX+PLUS II (legacy) |
| Lifecycle Status | β | Obsolete - last time buy was late 1990s |