EP910LC-40H vs EP910LC-40 Comparison

Detailed side-by-side comparison of EP910LC-40H by Altera and EP910LC-40 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910LC-40H EP910LC-40
Brand Altera Rochester Electronics
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.95 $52.00
Family Classic EPLD (EP910) β€”
Macro Cells 24 β€”
Usable Gates 450 450
Logic Elements 24 macro cells / expandable to 48 via expander terms β€”
Propagation Delay (tPD) 40 ns max 40 ns
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (single supply)
Supply Current (ICC) Low-power CMOS, typical ICC < 100 mA β€”
Technology CMOS, UV-erasable EPROM CMOS EPROM
Package 40-pin Ceramic DIP (CDIP-40), JEDEC standard PQCC-44 (Plastic Leaded Chip Carrier, J-lead)
Mounting Type Through-Hole (THT) β€”
Operating Temperature -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] β€”
Speed Grade -40 (40 ns tPD) β€”
Programming Method UV-erase + EPROM program, ~100 erase cycles Altera Logic Programmer (PLAD-J), 4-wire serial
I/O Pins [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] β€”
RoHS Status [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] Not applicable (legacy)
Manufacturer β€” Rochester Electronics (Altera original)
Device Family β€” Altera Classic EPLD - EP910
Product Type β€” EPLD (Erasable Programmable Logic Device)
Macrocells β€” 24
Logic Array Blocks β€” 2 (12 macrocells each)
Maximum Toggle Frequency (fMAX) β€” 25 MHz
User I/O Pins β€” 36
Dedicated Inputs β€” 4
Operating Temperature (Commercial) β€” 0 C to +70 C
Lead-Free Status β€” Not applicable

Datasheets & Resources

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