EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
MPN: EP910LC-40 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $72.67 | $72.67 |
| 10 | $70.5 | $705.00 |
| 100 | $65 | $6,500.00 |
| 500 | $58 | $29,000.00 |
| 1,000 | $52 | $52,000.00 |
EP910LC-40 Overview
An EPLD (Erasable Programmable Logic Device) is a type of non-volatile programmable logic that combines multiple PAL/GAL-like macrocell blocks on a single CMOS die. EPLDs sit in the hierarchy below modern CPLDs and FPGAs: macrocell -> PLD -> EPLD -> CPLD -> FPGA -> programmable logic -> semiconductor. Compared with bipolar PALs, EPLDs deliver lower power (CMOS), higher density (24 macrocells versus 8-16 in early PALs), and reprogrammability using either UV-erasable EPROM cells (windowed ceramic packages) or one-time-programmable EPROM cells (windowless plastic packages).
Key features of the EP910LC-40 include 450 usable gates, 24 macrocells distributed across two logic blocks, a 40ns worst-case pin-to-pin propagation delay (tPD) at 5V, 25 MHz maximum toggle frequency, 36 user I/O pins, and 4 dedicated inputs. Architecture is a sum-of-products AND/OR array driving 24 D-type flip-flops with individual preset/reset, J-lead PQCC-44 surface-mount package, 5V single-supply operation, and CMOS power consumption typically under 200 mW. A pin-compatible industrial-temperature grade EP910LI-40 also exists for -40C to +85C deployments.
The EP910 architecture combines a global interconnect with two Logic Array Blocks (LABs), each containing 12 macrocells fed by a programmable AND array. Configuration is stored in on-chip EPROM cells, so the device retains its pattern through power cycles without external boot memory - a key advantage over SRAM-based FPGAs of the era. Programming is performed using an Altera Logic Programmer (e.g., PLAD-J, PLAD-32) via the JTAG-like 4-wire serial interface, and the pattern can be erased with UV light through a quartz window (ceramic variants) or locked with security bit in windowless plastic variants.
Typical applications for the EP910LC-40 include industrial control glue logic, address decoding for microprocessor and DSP buses, peripheral interface adaptation, vintage PC chipset replacement (e.g., ISA bus glue logic, DMA controller state machines), retro computing and arcade board repair, telecom backplane glue logic, and legacy test equipment. Its 36 I/O pins and 24 flip-flops are well matched to bus-controller state machines and small synchronous interfaces where a few PALs would otherwise be required.
When designing with this device, note that 5V CMOS input thresholds are not 3.3V-tolerant - level shifting is required to interface with modern 3.3V logic. The PQCC-44 J-lead footprint needs a socket or careful reflow profile; the package is not pin-compatible with PLCC-44 sockets unless a J-to-PCB adaptor is used. Use the Altera MAX+PLUS II or classic A+PLUS design software for schematics, synthesis and programming file generation; modern toolchains can target EP910 via third-party synthesis flows.
Drop-in alternatives for EP910LC-40 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LC-40 (same form factor and footprint) β differing in Package, Technology, Propagation Delay (tPD), Mounting Type, Supply Voltage (VCC).
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP910LC-30
β Drop-Inβ In Stock
$22.5 / Unit
View Datasheet βEP910LC-35
β Drop-Inβ In Stock
$18.75 / Unit
View Datasheet βEP910LC-25
β Drop-Inβ In Stock
$2.2 / Unit
View Datasheet βEP910LC-32
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEP910LI-45
β Drop-Inπ Reference alternative (not in catalog)
EP910LC-40 Maximum Ratings & Electrical Characteristics
| Manufacturer | Rochester Electronics (Altera original) |
| Device Family | Altera Classic EPLD - EP910 |
| Product Type | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 450 |
| Macrocells | 24 |
| Logic Array Blocks | 2 (12 macrocells each) |
| Propagation Delay (tPD) | 40 ns |
| Maximum Toggle Frequency (fMAX) | 25 MHz |
| User I/O Pins | 36 |
| Dedicated Inputs | 4 |
| Supply Voltage (VCC) | 5 V (single supply) |
| Technology | CMOS EPROM |
| Package | PQCC-44 (Plastic Leaded Chip Carrier, J-lead) |
| Operating Temperature (Commercial) | 0 C to +70 C |
| Programming Method | Altera Logic Programmer (PLAD-J), 4-wire serial |
| RoHS Status | Not applicable (legacy) |
| Lead-Free Status | Not applicable |
EP910LC-40 Pin Configuration
| Pin 1 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 2 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 3 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 4 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 5 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 6 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 7 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 8 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 9 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 10 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 11 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 14 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 15 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 16 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 17 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 18 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 19 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 20 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 21 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 22 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 23 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 24 | IN β Dedicated input pin |
| Pin 25 | IN β Dedicated input pin |
| Pin 26 | IN β Dedicated input pin |
| Pin 27 | IN β Dedicated input pin |
| Pin 28 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 29 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 30 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 31 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 32 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 33 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 34 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 35 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 36 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 37 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 38 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 39 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 40 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 41 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 42 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 43 | I/O β Bidirectional I/O pin (macrocell input/output) |
| Pin 44 | VCC β +5V supply voltage |
Typical Applications
EP910LC-40 is suitable for 6 applications: Legacy Industrial Glue Logic, Vintage PC / Arcade Board Repair, Address Decoding for Microprocessor / DSP Buses, Peripheral Interface Adapters, Telecom Backplane Glue Logic, Legacy Test and Measurement Equipment.
Legacy Industrial Glue Logic
The EP910LC-40 fits legacy industrial glue logic because its 24 macrocells and 450 usable gates can replace three to five discrete 22V10 PALs while drawing under 200 mW from a 5V rail. The 40ns propagation delay comfortably handles 8-bit ISA, STD-32 and VME bus control state machines. The PQCC-44 J-lead package is still common on 1990s Eurocard PLC and motor-drive backplanes, so direct PCB repair is feasible without re-spinning the board.
Recommended
Vintage PC / Arcade Board Repair
The EP910LC-40 suits vintage PC and arcade board repair because it is the original Altera part installed on 1980s-1990s motherboards, sound boards and arcade game logic. Its windowless plastic PQCC-44 case and one-time-programmable EPROM cells exactly match the original BOM, so swapping in a fresh Rochester-stocked EP910LC-40 restores a board to factory function. Design teams can also pre-program the part with legacy JEDEC files generated by Altera A+PLUS.
Recommended
Address Decoding for Microprocessor / DSP Buses
The EP910LC-40 fits microprocessor and DSP address-decoding roles because its 24 macrocells provide ample sum-of-products terms to decode full 16- or 20-bit address spaces with chip-select outputs. The 36 user I/O pins can drive multiple peripheral enables simultaneously, replacing a stack of 74LS138 / 74LS139 decoder ICS. At 40ns tPD, it comfortably inserts behind an 8 MHz 80188 or a 10 MHz TMS320C25 without setup-time penalties.
Recommended
Peripheral Interface Adapters
The EP910LC-40 fits peripheral-interface adaptation because its 24 flip-flops with preset/reset can sequence SCSI, GPIB and parallel-port handshakes that previously required discrete 74LS logic. The CMOS process gives clean 5V signal swings and low ground bounce, important for SCSI-1 single-ended buses. The PQCC-44 footprint is still pad-compatible with retro computing cards where the original Altera part has long since failed.
Recommended
Telecom Backplane Glue Logic
The EP910LC-40 fits telecom backplane glue logic because its 5V CMOS design matches legacy T1/E1 line card supplies, and its 24 macrocells can implement bus-arbitration state machines for small backplane clusters. The industrial-temperature variants (EP910LI family) share the same PQCC-44 footprint, allowing direct substitution on outdoor cabinets. At 40ns tPD the device easily handles standard 8 kHz DS0 framing logic.
Recommended
Legacy Test and Measurement Equipment
The EP910LC-40 fits legacy test equipment because it is the factory-original Altera EPLD installed in 1990s oscilloscope front-end multiplexers, logic-analyzer state sequencers and GPIB-controlled instrument mainboards. Its 36 I/O pins can fan out to multiple measurement channels, while 24 flip-flops implement precise timing generators. Using a fresh Rochester-stocked EP910LC-40 with the original JEDEC bitstream restores calibration without board rework.
Recommended
Recommended Products Summary
Engineering reference data for EP910LC-40 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LC-30 | EP910LC-35 | EP910LC-25 | EP910LC-32 | EP910LI-45 |
|---|---|---|---|---|---|---|
| Brand | Rochester Electronics (Altera original) | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics |
| Package | PQCC-44 (J-lead) | PQCC-44 (J-lead) - same | PQCC-44 (J-lead) - same | PQCC-44 (J-lead) - same | PQCC-44 (J-lead) - same | PQCC-44 (J-lead) - same |
| Propagation Delay (tPD) | 40 ns | 30 ns | 35 ns | 25 ns | 32 ns | 45 ns |
| Usable Gates | 450 | 450 | 450 | 450 | 450 | 450 |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| User I/O Pins | 36 | 36 | 36 | 36 | 36 | 36 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Temperature Grade | Commercial (0C to +70C) | Commercial | Commercial | Commercial | Commercial | Industrial (-40C to +85C) |
| Programming | Altera Logic Programmer / JEDEC | Altera Logic Programmer / JEDEC - same | Altera Logic Programmer / JEDEC - same | Altera Logic Programmer / JEDEC - same | Altera Logic Programmer / JEDEC - same | Altera Logic Programmer / JEDEC - same |
Key Differentiators
- Slower speed grade than newer EP910LC variants (vs EP910LC-30)
- Commercial temperature grade only (vs EP910LI-45)
- Windowless plastic J-lead package, one-time-programmable (vs EP910DC-40)
Design Notes
The EP910LC-40 uses a PQCC-44 J-lead plastic chip carrier with 1.27 mm lead pitch. When designing or repairing a board, ensure the PCB land pattern follows JEDEC MO-047 for PQCC-44 (overall body 16.5 mm x 16.5 mm). J-leads require either a PLCC-44 socket with J-pin adaptor or direct reflow soldering - standard PLCC sockets without an adaptor will not make reliable contact because J-leads have a different curvature radius than PLCC gull-wing leads.
The EP910LC-40 operates from a single 5V (VCC) supply with a 5V-tolerant CMOS input threshold - inputs are NOT 3.3V tolerant. When interfacing to modern 3.3V logic such as a Cortex-M microcontroller or modern CPLD, add a level-translator (e.g., 74HCT245 for outputs going INTO the EP910, or a resistive divider / TXS0108E for outputs coming OUT of the EP910). Bulk decoupling: 0.1 uF ceramic + 10 uF tantalum within 5 mm of VCC pin 44. Estimated ICC at 25 MHz toggle is 80-120 mA typical, 200 mA worst-case, so verify supply current budget.
Do not confuse EP910LC-40 (PQCC-44) with EP910PC-40 (PDIP-40) or EP910DC-40 (ceramic-windowed DIP-40) - they share the EP910 family but have different pin counts and footprints, so they are NOT pin-compatible. Likewise, do not substitute an EP910LC-40 with an EP610LC-25 even if the package looks similar - the EP610 has only 16 macrocells vs 24, so the JEDEC bitstream will not fit. Always re-synthesise and re-fit the design when changing density. Keep security-bit usage in mind: once enabled, the EP910LC-40 cannot be re-read, only bulk-erased (windowed variants only) or discarded.
Compliance Information
Legacy part with original Altera bill of materials predates RoHS requirements. RoHS compliant equivalents may exist in the EP910LC-30 / EP910LC-35 family if the modernised Rochester wafer run is lead-free; otherwise choose a modern CPLD for RoHS-compliant new designs.
