EP910LC-40T vs EP910LC-35T Comparison
Detailed side-by-side comparison of EP910LC-40T by Altera and EP910LC-35T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910LC-40T
EP910LC-40T - Classic EPLD, 24 Macrocells, 40ns, PLCC-44 | Altera
EP910LC-40T ObsoleteSpecification Comparison
| Parameter | EP910LC-40T | EP910LC-35T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.40 | $28.90 |
| Family | Altera Classic EPLD | Classic EPLD (EP910) |
| Equivalent Gates | 450 gates | β |
| Macrocells | 24 | 24 |
| Logic Array Blocks | 4 Logic Expandable AND-OR arrays | β |
| User I/O Pins | 36 | 36 |
| Propagation Delay (tPD) | 40 ns | 35 ns |
| Maximum Frequency (fMAX) | 25 MHz | β |
| Supply Voltage | 5 V (4.75 V to 5.25 V) | β |
| Technology | CMOS, UV-erasable | β |
| Package | PLCC-44 (PQCC44) | PLCC-44 (J-lead) |
| Operating Temperature | -40 C to +85 C (commercial, per -LC suffix family) | 0C to +70C (commercial) |
| Programming | Altera MAX+PLUS II / APLUS tools | Altera programming hardware + MAX+PLUS II |
| Erase/Reprogram Cycles | 100 (windowed UV-erase family) | β |
| Pin Count | 44 | β |
| Packaging Option | Tape and Reel (T suffix) | β |
| RoHS Status | [DATA_NEEDED: RoHS status - not stated in web data] | [DATA_NEEDED: RoHS status not in verified data] |
| Logic Capacity | β | 450 usable gates |
| Maximum Operating Frequency | β | 28.6 MHz |
| Supply Voltage (VCC) | β | 5 V |
| Process Technology | β | CMOS (EPROM-based) |
| Erasure Method | β | UV-erasable window (ceramic package) / OTP (plastic) |
| Mounting Type | β | Surface Mount (PLCC socket or solder) |
| MSL Level | β | MSL 3 (168 hours) |