EP910LC-35T - 24-Macrocell 35ns CMOS Classic EPLD | Altera
MPN: EP910LC-35T ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $42 | $42.00 |
| 10 | $38.5 | $385.00 |
| 100 | $34.75 | $3,475.00 |
| 500 | $31.2 | $15,600.00 |
| 1,000 | $28.9 | $28,900.00 |
EP910LC-35T Overview
A Classic EPLD is a non-volatile, UV-erasable programmable logic device positioned historically between simple PAL/GAL devices and modern CPLDs/FPGAs. In the system hierarchy, EPLDs belong to the programmable logic family, sitting above discrete logic ICs and below today's high-density FPGAs. They are typically used for glue logic, address decoding, state machines, and bus interfacing in 5V legacy designs where deterministic pin-to-pin timing is required.
Key features of the EP910LC-35T include 24 macrocells arranged in logic blocks, 36 user I/O pins, in-system programmability via the Altera EPROM-based architecture, and a 28.6MHz maximum operating frequency. The device consumes CMOS-level standby current, supports JTAG-compatible boundary-scan testing on selected package variants, and provides tri-state output control on every macrocell for bus-oriented applications.
The EP910LC-35T utilizes Altera's Classic architecture combining a global interconnect with local macrocell feedback, allowing each macrocell to implement combinatorial or registered logic with configurable output polarity. The 35ns speed grade reflects the tPD (pin-to-pin delay) at 5V VCC, which is adequate for peripheral decode and slow-state-machine use cases rather than high-speed datapath logic.
Typical applications include 5V address decoding in legacy microprocessor boards, glue-logic replacement of discrete 74LS/74HC gates, bus-interfacing adapters between 8-bit and 16-bit peripherals, and replacement of multiple PAL/GAL devices on industrial control boards. The PLCC-44 footprint also makes it a popular choice for socketed field-replacement scenarios.
When designing with this device, ensure the design fits within 24 macrocells and uses the supplied Altera MAX+PLUS II development tools (legacy) for fitting, simulation, and programming file generation. Note that Classic EPLDs are mature/OEM-only devices; current production is limited to authorized distributors stocking legacy inventory.
This page synthesizes distributor pricing, legacy cross-references, package-compatible alternatives, and practical design notes for engineers maintaining or replacing EP910-series devices in long-lifecycle equipment.
Drop-in alternatives for EP910LC-35T — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LC-35T (same form factor and footprint) — differing in Package, Propagation Delay (tPD), Mounting Type, Technology, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910LC-35
✅ Drop-In✓ In Stock
$18.75 / Unit
View Datasheet →EP910LC-35H
✅ Drop-In✓ In Stock
$25 / Unit
View Datasheet →EP910LC-32
✅ Drop-In✓ In Stock
$9.85 / Unit
View Datasheet →EP910LC-30
✅ Drop-In✓ In Stock
$22.5 / Unit
View Datasheet →EP910LC-25
✅ Drop-In✓ In Stock
$2.2 / Unit
View Datasheet →EP910LC-35T Maximum Ratings & Electrical Characteristics
| Family | Classic EPLD (EP910) |
| Logic Capacity | 450 usable gates |
| Macrocells | 24 |
| Propagation Delay (tPD) | 35 ns |
| Maximum Operating Frequency | 28.6 MHz |
| Supply Voltage (VCC) | 5 V |
| User I/O Pins | 36 |
| Package | PLCC-44 (J-lead) |
| Process Technology | CMOS (EPROM-based) |
| Operating Temperature | 0C to +70C (commercial) |
| Erasure Method | UV-erasable window (ceramic package) / OTP (plastic) |
| Programming | Altera programming hardware + MAX+PLUS II |
| Mounting Type | Surface Mount (PLCC socket or solder) |
| MSL Level | MSL 3 (168 hours) |
EP910LC-35T Pin Configuration
| Pin 1 | I/O — User I/O macrocell pin |
| Pin 2 | I/O — User I/O macrocell pin |
| Pin 3 | I/O — User I/O macrocell pin |
| Pin 4 | I/O — User I/O macrocell pin |
| Pin 5 | I/O — User I/O macrocell pin |
| Pin 6 | I/O — User I/O macrocell pin |
| Pin 7 | I/O — User I/O macrocell pin |
| Pin 8 | I/O — User I/O macrocell pin |
| Pin 9 | I/O — User I/O macrocell pin |
| Pin 10 | GND — Ground reference |
| Pin 11 | I/O — User I/O macrocell pin |
| Pin 12 | I/O — User I/O macrocell pin |
| Pin 13 | I/O — User I/O macrocell pin |
| Pin 14 | I/O — User I/O macrocell pin |
| Pin 15 | I/O — User I/O macrocell pin |
| Pin 16 | I/O — User I/O macrocell pin |
| Pin 17 | I/O — User I/O macrocell pin |
| Pin 18 | I/O — User I/O macrocell pin |
| Pin 19 | I/O — User I/O macrocell pin |
| Pin 20 | I/O — User I/O macrocell pin |
| Pin 21 | VCC — +5V supply input |
| Pin 22 | I/O — User I/O macrocell pin |
| Pin 23 | I/O — User I/O macrocell pin |
| Pin 24 | I/O — User I/O macrocell pin |
| Pin 25 | I/O — User I/O macrocell pin |
| Pin 26 | I/O — User I/O macrocell pin |
| Pin 27 | I/O — User I/O macrocell pin |
| Pin 28 | I/O — User I/O macrocell pin |
| Pin 29 | I/O — User I/O macrocell pin |
| Pin 30 | I/O — User I/O macrocell pin |
| Pin 31 | GND — Ground reference |
| Pin 32 | I/O — User I/O macrocell pin |
| Pin 33 | I/O — User I/O macrocell pin |
| Pin 34 | I/O — User I/O macrocell pin |
| Pin 35 | I/O — User I/O macrocell pin |
| Pin 36 | I/O — User I/O macrocell pin |
| Pin 37 | I/O — User I/O macrocell pin |
| Pin 38 | I/O — User I/O macrocell pin |
| Pin 39 | I/O — User I/O macrocell pin |
| Pin 40 | I/O — User I/O macrocell pin |
| Pin 41 | I/O — User I/O macrocell pin |
| Pin 42 | VCC — +5V supply input |
| Pin 43 | DCLK — Dedicated clock input for global clock network |
| Pin 44 | OE — Global output enable (active low for some macros) |
Typical Applications
EP910LC-35T is suitable for 7 applications: Legacy Microprocessor Address Decoding, Glue-Logic Consolidation, Industrial Control State Machines, VME / ISA Bus Interface Adapters, Replacement for Multiple PAL/GAL Devices, Long-Lifecycle Military/Aerospace Sustainment, Educational and Prototyping Platforms.
Legacy Microprocessor Address Decoding
The EP910LC-35T's 24 macrocells and 35ns tPD make it well-suited to decode 5V microprocessor address buses (8086, 68000, Z80) into chip-select and peripheral-enable signals. In a typical IBM-PC-style design the EP910LC-35T replaces 6 to 10 discrete 74LS138 / 74LS139 decoder ICs, freeing board area and reducing propagation skew between selects. The 28.6 MHz fMAX comfortably covers ISA-bus timing, where bus cycles complete in roughly 250 ns, leaving ample margin for address-decode glue logic. Using one EPLD instead of multiple decoders also consolidates the BOM and simplifies ECO changes via software reprogramming rather than wire-wrap rework.
Recommended
Glue-Logic Consolidation
Designers traditionally implement board-level glue logic with banks of 74LS00, 74LS244, and 74LS373 parts; the EP910LC-35T can absorb 20 to 30 discrete gates into a single 5V PLCC-44 device, reducing board area, power, and inventory. With 24 macrocells and 36 I/O pins, the part supports mixed combinatorial and registered functions, including bus buffers, latches, and parity generators, all on the same silicon. CMOS-level quiescent current keeps thermal dissipation low, and the 35ns tPD is adequate for asynchronous peripheral interfaces where sub-microsecond response is sufficient.
Recommended
Industrial Control State Machines
The EP910LC-35T is a strong fit for Moore or Mealy state machines driving relays, solenoids, and motor-control signals on industrial controllers, where deterministic 35ns propagation simplifies hazard analysis. With 24 macrocells it can implement state diagrams of up to 16 to 20 states with output-decoded actions, and the 36 user I/O pins comfortably handle multi-axis machine I/O. Operating from a single 5V rail and consuming CMOS standby current, it can be battery-backed for power-quality event logging. The PLCC-44 socket option also simplifies field replacement in deployed equipment, an important consideration for long-lifecycle industrial lines.
Recommended
VME / ISA Bus Interface Adapters
For 5V VMEbus and ISA backplanes, the EP910LC-35T serves as a protocol bridge or bus arbiter, converting legacy DMA handshakes and interrupt acknowledge sequences into board-local control signals. Its 35ns tPD matches VMEbus single-cycle access timing (~250ns cycle) without violating setup/hold margins on DTACK and IRQ lines. The 36 I/O pins allow mapping of full 16-bit data plus control and status, and the registered macrocells can implement state-based arbitration. CMOS power consumption makes it suitable for densely-populated backplanes with strict airflow budgets.
Recommended
Replacement for Multiple PAL/GAL Devices
Many legacy boards use two to four 20-pin or 24-pin PAL/GAL devices to implement decode, latch, and counter logic. The EP910LC-35T with 24 macrocells can absorb up to four 16V8-class GALs on a single PLCC-44 footprint, simplifying board rework and inventory. Designers can use Altera MAX+PLUS II to compile multiple ABEL/CUPL source files into one EP910LC design, shortening firmware migration. This consolidation also reduces socket count and improves mean time between failure for deployed systems.
Recommended
Long-Lifecycle Military/Aerospace Sustainment
Avionics, naval, and ground-vehicle platforms built in the 1990s still require field-replacement of damaged EP910LC-35T devices on PLCC-44 footprints. Authorized legacy distributors such as Rochester Electronics maintain tested inventory and DSCC-qualified date codes for these programs. The 35ns tPD and 24 macrocells cover typical MIL-STD-1553 and ARINC-429 decoder glue logic; CMOS standby current simplifies thermal budgets in sealed enclosures. Designers often pair the EP910LC-35T with EP910LC-35H screened variants for high-reliability assemblies.
Recommended
Educational and Prototyping Platforms
University digital-logic labs and FPGA prototyping trainers continue to use the EP910LC-35T because of its simple Altera Classic architecture and PLCC-44 socketed form factor, which tolerates repeated insertion cycles. With 24 macrocells and 450 usable gates, students can implement counters, FSMs, and small CPUs without the complexity of modern HDL toolchains. The 5V supply tolerates the wide variety of legacy breadboard peripherals used in coursework. The PLCC-44 socket also simplifies hands-on reprogramming during lab exercises.
Recommended
Recommended Products Summary
Engineering reference data for EP910LC-35T — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LC-35 | EP910LC-35H | EP910LC-32 | EP910LC-30 | EP910LC-25 |
|---|---|---|---|---|---|---|
| Package | PLCC-44 | PLCC-44 (same) | PLCC-44 (same) | PLCC-44 (same) | PLCC-44 (same) | PLCC-44 (same) |
| Brand | Altera | Altera (same) | Altera (same) | Altera (same) | Altera (same) | Altera (same) |
| Propagation Delay (tPD) | 35 ns | 35 ns (identical) | 35 ns (identical) | 32 ns (-9%) | 30 ns (-17%) | 25 ns (-40%) |
| Maximum Frequency | 28.6 MHz | 28.6 MHz (identical) | 28.6 MHz (identical) | ~31 MHz | ~33 MHz | ~40 MHz |
| Macrocells | 24 | 24 (identical) | 24 (identical) | 24 (identical) | 24 (identical) | 24 (identical) |
| Usable Gates | 450 | 450 (identical) | 450 (identical) | 450 (identical) | 450 (identical) | 450 (identical) |
| User I/O | 36 | 36 (identical) | 36 (identical) | 36 (identical) | 36 (identical) | 36 (identical) |
| Supply Voltage | 5 V | 5 V (identical) | 5 V (identical) | 5 V (identical) | 5 V (identical) | 5 V (identical) |
| Shipping Packaging | Tape & Reel ('T' suffix) | Tube (no suffix) | Tube/Tray (H = burn-in) | Tube (typical) | Tube (typical) | Tube (typical) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Tape-and-Reel packaging for high-volume SMT assembly (vs EP910LC-35 (Tube))
- Industry-standard 35ns speed grade for legacy timing budgets (vs EP910LC-25 (25ns))
- 24 macrocells - the highest-capacity 5V Classic EPLD in PLCC-44 (vs Altera EP610PC (24-pin, 16 macrocells))
Design Notes
The EP910LC-35T operates from a single 5V +/-10% supply and draws CMOS-level quiescent current in standby, but dynamic current increases with toggle frequency. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of each VCC pin (pins 21 and 42) and a bulk 10 uF tantalum or aluminum electrolytic capacitor at the board's 5V entry point. Do not share the EP910LC-35T's decoupling with high-current switching loads such as relay coils or motor drivers, since the resulting supply ripple can couple into the EPLD's threshold logic.
Route all 36 user I/O traces with matched impedance when driving buses longer than ~50 mm, and add 22-33 ohm series-termination resistors at the EP910LC-35T outputs for signals faster than 8 ns rise time. Keep the dedicated DCLK input (pin 43) trace short and shielded with a ground guard on both sides to minimize jitter. Use a PLCC-44 socket (e.g., 3M Textool or Aries) if field replacement is expected; for production, solder directly with J-lead reflow at peak temperature 235C.
Do not assume the EP910LC-35T is hot-swap compatible; its I/O buffers were not designed for live insertion, and powering the device before VCC ramps can trigger latchup. Always sequence VCC before driving any input signal, and ensure the global OE (pin 44) is de-asserted during power-up to keep outputs in high-impedance. Another common pitfall is over-driving macrocell I/O: the EP910LC-35T sinks/ sources 8 mA per pin (24 mA per bank limit), so fan-out to multiple 74LS loads may require external buffers such as 74HC245.
Maintain a continuous ground plane on the layer immediately beneath the EP910LC-35T to provide low-inductance return paths for switching outputs. Keep analog and digital grounds separate if mixing with adjacent analog circuitry, joining them only at the board's main ground entry point. For noisy environments (relay panels, motor drives), add a ferrite bead on the EP910LC-35T's VCC pin 21 input to suppress common-mode noise; bypass capacitors should still be placed close to the package body.
Compliance Information
RoHS, REACH, lead-free, halogen-free, and conflict-minerals status were not present in the verified web data as of 2026-09-10. Classic EPLDs were typically released before RoHS took full effect; please request a compliance certificate from Rochester Electronics or the authorized distributor for the specific date code you receive. AEC-Q100 is not applicable because the EP910LC-35T is a commercial-grade 0C to +70C part.
