EP910LC-40T - Classic EPLD, 24 Macrocells, 40ns, PLCC-44 | Altera
MPN: EP910LC-40T ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.8 | $1,380.00 |
| 500 | $11.95 | $5,975.00 |
| 1,000 | $10.4 | $10,400.00 |
EP910LC-40T Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architecture of PAL/GAL with on-chip EEPROM or EPROM storage. Within the broader programmable logic hierarchy, CPLDs sit alongside FPGAs (Field-Programmable Gate Arrays) and SPLDs (Simple PLDs), with CPLDs typically offering faster deterministic pin-to-pin timing, lower power consumption, and instant-on behavior versus SRAM-based FPGAs that require a configuration bitstream. CPLDs are widely used for I/O expansion, bus interfacing, address decoding, and state-machine implementation in industrial, telecom, and military systems where deterministic timing is critical.
Key features of the EP910LC-40T include 24 macrocells organized into four Logic Expandable AND-OR arrays, 36 dedicated I/O pins, a 40 ns maximum propagation delay (tPD), 25 MHz typical fMAX, and an erase/rewrite endurance of 100 cycles (windowed UV-erase device). The device is programmed using the Altera MAX+PLUS II or earlier APLUS development tools via a dedicated programming hardware interface.
The architecture uses a programmable AND-OR array driving macrocell flip-flops with programmable output polarity. Each macrocell provides D, T, JK, or SR flip-flop modes with a dedicated product-term clock and asynchronous clear, giving the device deterministic timing suitable for replacing multiple discrete 22V10/16V8-style PALs.
Typical applications include bus-interface glue logic for legacy 8086/Motorola 68k microprocessor systems, address decoding and chip-select generation, industrial control state machines, and replacement of multiple discrete TTL/CMOS logic gates. The wide supply tolerance and CMOS process make it well suited to noisy industrial environments.
When designing with this part, note that it is a UV-erasable windowed device (no -J ceramic-window variant noted in this -LC family code, but the EP910 family includes windowed parts). Designers should verify programming socket compatibility and consider modern MAX II/MAX V CPLDs for new designs.
This page synthesizes distributor availability, drop-in alternative MPNs from the same EP910 family, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EP910LC-40T — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LC-40T (same form factor and footprint) — differing in Package, Technology, Propagation Delay (tPD), Family, Supply Voltage (VCC).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910LC-40
✅ Drop-In✓ In Stock
$52 / Unit
View Datasheet →EP910LC-35T
✅ Drop-In✓ In Stock
$28.9 / Unit
View Datasheet →EP910LC-35
✅ Drop-In✓ In Stock
$18.75 / Unit
View Datasheet →EP910LC-30T
✅ Drop-In✓ In Stock
$7.1 / Unit
View Datasheet →EP910LC-25
✅ Drop-In✓ In Stock
$2.2 / Unit
View Datasheet →EP910LC-40T Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Equivalent Gates | 450 gates |
| Macrocells | 24 |
| Logic Array Blocks | 4 Logic Expandable AND-OR arrays |
| User I/O Pins | 36 |
| Propagation Delay (tPD) | 40 ns |
| Maximum Frequency (fMAX) | 25 MHz |
| Supply Voltage | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS, UV-erasable |
| Package | PLCC-44 (PQCC44) |
| Operating Temperature | -40 C to +85 C (commercial, per -LC suffix family) |
| Programming | Altera MAX+PLUS II / APLUS tools |
| Erase/Reprogram Cycles | 100 (windowed UV-erase family) |
| Pin Count | 44 |
| Packaging Option | Tape and Reel (T suffix) |
EP910LC-40T Pin Configuration
| Pin 1 | I/O — User I/O pin (macrocell) |
| Pin 2 | I/O — User I/O pin (macrocell) |
| Pin 3 | I/O — User I/O pin (macrocell) |
| Pin 4 | I/O — User I/O pin (macrocell) |
| Pin 5 | I/O — User I/O pin (macrocell) |
| Pin 6 | I/O — User I/O pin (macrocell) |
| Pin 7 | I/O — User I/O pin (macrocell) |
| Pin 8 | I/O — User I/O pin (macrocell) |
| Pin 9 | I/O — User I/O pin (macrocell) |
| Pin 10 | GND — Ground |
| Pin 11 | I/O — User I/O pin (macrocell) |
| Pin 12 | I/O — User I/O pin (macrocell) |
| Pin 13 | I/O — User I/O pin (macrocell) |
| Pin 14 | I/O — User I/O pin (macrocell) |
| Pin 15 | I/O — User I/O pin (macrocell) |
| Pin 16 | I/O — User I/O pin (macrocell) |
| Pin 17 | I/O — User I/O pin (macrocell) |
| Pin 18 | I/O — User I/O pin (macrocell) |
| Pin 19 | I/O — User I/O pin (macrocell) |
| Pin 20 | I/O — User I/O pin (macrocell) |
| Pin 21 | VCC — +5V supply |
| Pin 22 | I/O — User I/O pin (macrocell) |
| Pin 23 | I/O — User I/O pin (macrocell) |
| Pin 24 | I/O — User I/O pin (macrocell) |
| Pin 25 | I/O — User I/O pin (macrocell) |
| Pin 26 | I/O — User I/O pin (macrocell) |
| Pin 27 | I/O — User I/O pin (macrocell) |
| Pin 28 | I/O — User I/O pin (macrocell) |
| Pin 29 | I/O — User I/O pin (macrocell) |
| Pin 30 | I/O — User I/O pin (macrocell) |
| Pin 31 | GND — Ground |
| Pin 32 | I/O — User I/O pin (macrocell) |
| Pin 33 | I/O — User I/O pin (macrocell) |
| Pin 34 | I/O — User I/O pin (macrocell) |
| Pin 35 | I/O — User I/O pin (macrocell) |
| Pin 36 | I/O — User I/O pin (macrocell) |
| Pin 37 | I/O — User I/O pin (macrocell) |
| Pin 38 | I/O — User I/O pin (macrocell) |
| Pin 39 | I/O — User I/O pin (macrocell) |
| Pin 40 | I/O — User I/O pin (macrocell) |
| Pin 41 | VCC — +5V supply |
| Pin 42 | I/O — User I/O pin (macrocell) |
| Pin 43 | DED_IN — Dedicated input pin |
| Pin 44 | DED_IN — Dedicated input pin |
Typical Applications
EP910LC-40T is suitable for 6 applications: Legacy Microprocessor Bus Glue Logic, Address Decoding and Chip-Select Generation, Industrial Control State Machines, TTL/CMOS Logic Gate Consolidation, Legacy Telecom Backplane Interface, Replacement of Obsolete 22V10/16V8 PALs.
Legacy Microprocessor Bus Glue Logic
The EP910LC-40T is well suited to legacy 8086, 80286, and Motorola 68000-series microprocessor bus-interface glue logic, where deterministic pin-to-pin timing is critical. Its 40 ns tPD and 24 macrocells provide ample capacity to consolidate multiple discrete 22V10/16V8 PALs into a single device for address decoding, chip-select generation, and bus arbitration. The device's CMOS process and 5V single-supply operation integrate cleanly with classic TTL logic families. Compared to an FPGA, the EP910LC-40T offers instant-on behavior (no configuration bitstream required), making it ideal for boot-time bus control. The PLCC-44 footprint also supports through-hole sockets common in legacy test fixtures and industrial backplane designs where component replacement is expected.
Recommended
Address Decoding and Chip-Select Generation
With 24 macrocells organized across 4 Logic Expandable AND-OR arrays, the EP910LC-40T can implement a large number of independent chip-select signals for memory-mapped peripherals, replacing an entire board-full of discrete 74LS138 decoders and PALs. The device's deterministic tPD of 40 ns makes it straightforward to calculate chip-select access times relative to the system clock, and the 36 user I/O pins provide sufficient fan-out for typical 8-bit and 16-bit microprocessor systems. Because the EP910LC-40T is non-volatile, chip-select logic is available at power-on with zero configuration delay - critical for cold-boot systems where peripherals must be deselected before the CPU fetches its first instruction.
Recommended
Industrial Control State Machines
The EP910LC-40T is widely deployed in industrial control systems for state-machine implementation, particularly in PLCs, motor controllers, and process-control front-ends where its CMOS process and 5V supply provide good noise immunity in factory environments. Each macrocell supports D, T, JK, and SR flip-flop modes with asynchronous clear, giving the designer flexibility to implement Moore or Mealy state machines with predictable timing. The commercial operating-temperature range (-40C to +85C family code) and PLCC-44 package with through-hole socket compatibility make field replacement straightforward. Designers appreciate the deterministic 40 ns propagation delay when certifying safety-related control logic to industrial standards.
Recommended
TTL/CMOS Logic Gate Consolidation
A common use case for the EP910LC-40T is replacing multiple discrete 74LS00, 74LS138, 74LS151, and other small- and medium-scale TTL/CMOS logic packages with a single programmable device. The 24 macrocells and 36 user I/O pins are sufficient to consolidate 5-10 SSI/MSI packages into one EP910LC-40T, reducing board area, power consumption, and inventory burden. The 5V single-supply operation interfaces directly with TTL logic levels without level shifters. Although the 40 ns tPD is slower than 74AS/74F TTL, it is acceptable for non-critical-path glue logic, and the deterministic timing simplifies system-level timing analysis compared with discrete gate delays.
Recommended
Legacy Telecom Backplane Interface
Telecom backplane systems built in the 1990s frequently used Altera Classic EPLDs such as the EP910LC-40T for low-level backplane glue logic, including bus arbitration, parity generation/checking, and interrupt steering. The device's CMOS process gives low power consumption suitable for densely populated backplane cards, while the 5V supply matches legacy backplane voltages. The 36 user I/O pins and 24 macrocells are well matched to typical 8-16 line interface functions. With telecom systems often running for decades, the EP910LC-40T remains in active demand for field-replacement spares, sourced primarily through Rochester Electronics which specializes in long-lifecycle semiconductor support.
Recommended
Replacement of Obsolete 22V10/16V8 PALs
The EP910LC-40T serves as a modern consolidation replacement for designers maintaining legacy systems that originally used multiple 22V10 or 16V8 PALs. With 24 macrocells and 450 equivalent gates, one EP910LC-40T replaces 2-3 typical 22V10 PALs while adding flexibility for future logic modifications through UV-erase/reprogram cycles. Designers can also use the device as a unified platform during incremental board redesigns, allowing partial migration to newer logic. Although 22V10 emulation does not consume all 24 macrocells, the unused macrocells can implement additional decoding or status logic, improving overall board integration while maintaining backwards compatibility with existing test patterns.
Recommended
Recommended Products Summary
Engineering reference data for EP910LC-40T — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LC-40 | EP910LC-35T | EP910LC-35 | EP910LC-30T | EP910LC-25 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-44 | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same |
| Propagation Delay (tPD) | 40 ns | 40 ns (identical) | 35 ns | 35 ns | 30 ns | 25 ns |
| Macrocells | 24 | 24 (same) | 24 | 24 | 24 | 24 |
| Equivalent Gates | 450 | 450 (same) | 450 | 450 | 450 | 450 |
| User I/O Pins | 36 | 36 (same) | 36 | 36 | 36 | 36 |
| Supply Voltage | 5 V | 5 V (same) | 5 V | 5 V | 5 V | 5 V |
| Packaging Option | Tape and Reel | Tube | Tape and Reel | Tube | Tape and Reel | Tube |
Key Differentiators
- Identical silicon and pinout with tube-packaging option (vs EP910LC-40)
- Faster speed grade available in same package (vs EP910LC-35T)
- Drop-in replacement for entire speed-grade family (vs EP910LC-25)
Design Notes
The EP910LC-40T is a UV-erasable windowed Classic EPLD - it requires a quartz window package (or in this LC-family, a windowless plastic package that is one-time-programmable only) and a compatible Altera programming hardware. Designers using the EP910LC (PLCC, no window) variant must pre-program before PCB assembly using a separate programming socket; field updates require device replacement. Verify programming method matches the package suffix - LC parts are typically OTP (one-time-programmable) while DC/ILC/JC variants include a ceramic window.
The EP910LC-40T operates from a single 5V supply with a tolerance of 4.75V to 5.25V per the Altera Classic EPLD datasheet. Decoupling should follow the manufacturer reference design: place a 0.1 uF ceramic capacitor close to each VCC pin (pins 21 and 41 in PLCC-44) and a 10 uF tantalum bulk capacitor at the board supply entry point. Estimated: with all 36 I/O pins switching at 5 MHz CMOS load, dynamic supply current may reach 30-50 mA; verify with bench measurement.
When laying out a PCB for the EP910LC-40T in a PLCC-44 socket, reserve at least 0.5 inch of copper-pour ground around the socket to provide thermal dissipation and EMI shielding. The PLCC-44 socket allows easy field replacement - critical for industrial and telecom systems where the EP910LC-40T may be in service for decades. Maintain 50 ohm characteristic impedance on clock traces connecting to the device, since the 40 ns tPD allows signal rise times around 4-6 ns at typical loads.
Unused I/O pins on the EP910LC-40T should be configured as outputs driving low (not left floating) to minimize supply current and reduce noise injection. Per Altera application notes, each floating input can draw leakage current and may oscillate, coupling noise into adjacent signal traces. Program unused pins in the MAX+PLUS II design file as 'Output Pin = GND' before generating the JEDEC programming file.
Compliance Information
Compliance status not explicitly stated in verified web data. Classic EPLD devices from the early-to-mid 1990s typically predate RoHS requirements. Contact Rochester Electronics for Declaration of Conformity if RoHS documentation is required. The part is classified as obsolete and not AEC-Q100 qualified.
