EP910LC44 vs EP910LI44 Comparison
Detailed side-by-side comparison of EP910LC44 by Altera and EP910LI44 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera
EP910LC44 β Last Time BuySpecification Comparison
| Parameter | EP910LC44 | EP910LI44 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.95 | $8.20 |
| Product Family | Classic EPLD (EP910 Series) | β |
| Manufacturer | Altera Corporation (now Intel PSG) | β |
| Device Type | Erasable Programmable Logic Device (EPLD) | β |
| Macrocells | 24 | 24 |
| Total Product Terms | 240 | β |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | β |
| Total Input Pins | 36 (12 dedicated + 24 I/O as inputs) | β |
| Global Clock Inputs | 2 | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (commercial), 4.5 V to 5.5 V (industrial) |
| Propagation Delay (LC grade) | [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] | β |
| Propagation Delay (LC-30 grade) | 33 ns (per EP910LC44-30 verified data) | β |
| Process Technology | CMOS | β |
| Package | 44-pin PLCC (J-leaded) | β |
| Operating Temperature | [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] | β |
| Programming Method | EPROM (erasable UV for ceramic; OTP for plastic PLCC) | Altera Logic Programmer card / Data I/O / third-party EPROM programmers |
| Architecture | AND-OR sum-of-products with programmable macrocell feedback | PAL-type, CMOS, One-Time-Programmable |
| Logic Compatibility | TTL-compatible CMOS I/O | β |
| RoHS Status | [DATA_NEEDED: not stated in verified data] | non-compliant (original PLCC-44 lead finish) |
| Family | β | Classic EPLD |
| Package Type | β | PLCC-44 (J-lead, surface mount) |
| Total Pins | β | 44 |
| Bidirectional I/O | β | 24 |
| Maximum Logic Inputs | β | 36 |
| Maximum Outputs | β | 24 |
| Flip-Flops | β | 24 |
| External Clocks | β | 2 |
| Maximum Propagation Delay | β | [DATA_NEEDED: tpd for unmarked speed grade; speed-grade suffix encodes value: -15 = 15 ns, -20 = 20 ns, -25 = 25 ns, -30 = 30 ns, -35 = 35 ns, -40 = 40 ns, -45 = 45 ns, -50 = 50 ns] |
| Operating Temperature (L grade) | β | -40 Β°C to +85 Β°C (industrial) |
| Technology | β | CMOS |
| Programmability | β | UV-erasable (windowed) or OTP |
| Mounting Type | β | Surface Mount (PLCC socket compatible) |