EP910LI-30 vs EP910LI-20 Comparison
Detailed side-by-side comparison of EP910LI-30 by Rochester Electronics and EP910LI-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP910LI-30
EP910LI-30 - 24-Macrocell EPLD, 30ns, PQCC44 | Rochester/Altera
EP910LI-30 ObsoleteSpecification Comparison
| Parameter | EP910LI-30 | EP910LI-20 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $49.50 | $19.95 |
| Family | Altera Classic EPLD EP910 | Altera Classic EPLD |
| Device Type | Erasable Programmable Logic Device (EPLD) | β |
| Macrocells | 24 | 24 |
| Equivalent Gates | 450 | β |
| Propagation Delay (tPD) | 30 ns | β |
| Supply Voltage (VCC) | 5 V Β±5% (4.75 V to 5.25 V) | 5 V |
| Supply Current (ICC) | [DATA_NEEDED: ICC standby/active] | β |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| Process Technology | CMOS EPROM, UV-erasable | β |
| Package | 44-pin PQCC / PLCC-44 (J-lead) | 40-pin Ceramic DIP (Windowed) |
| Mounting Type | Surface Mount (socket recommended for UV erasure) | β |
| Dedicated Inputs | 10 | 16 |
| I/O Pins | 22 | 24 |
| Programming Method | Altera EPLD programming algorithm / MAX+PLUS II legacy support | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance not verified in scraped data] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Manufacturer (Original) | Altera (now Intel PSG) | β |
| Current Stocking Channel | Rochester Electronics (authorized aftermarket) | β |
| Maximum Operating Frequency | β | 62 MHz |
| Propagation Delay (tpd) | β | 20 ns |
| Technology | β | CMOS, UV-erasable |
| Package Type | β | Through-Hole, Ceramic DIP with Quartz Window |
| Temperature Grade | β | Industrial (-40C to +85C) |
| Pin Count | β | 40 |
| Logic Family | β | EPLD (Erasable PLD) |
| Architecture | β | Sum-of-products macrocell |
| Pin/Package Compatibility | β | Pin-compatible across EP910 family |