EP910LI-20 - Classic EPLD 24 Macrocells, 20ns | Altera
MPN: EP910LI-20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $27.5 | $2,750.00 |
| 500 | $23.25 | $11,625.00 |
| 1,000 | $19.95 | $19,950.00 |
EP910LI-20 Overview
An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that combines the non-volatility and reprogrammability of UV-erasable EPROM technology with the macrocell-based logic density of early PLDs. EPLDs sit in the hierarchy: programmable logic -> PLD -> EPLD -> CMOS EPLD -> logic integration IC, predating modern CPLDs and FPGAs. The Classic family was Altera's flagship high-speed, low-power logic integration platform in the late 1980s and 1990s.
The EP910LI-20 is fabricated on an advanced CMOS process that delivers low static power consumption typical of the Classic family, typically 200 mA ICC at military/industrial operating conditions. The device is pin-compatible across the EP910 family, allowing designers to swap speed grades (EP910LC-40, EP910LC-35, EP910LC-30) without PCB rework. Each macrocell offers configurable combinatorial or registered logic, with dedicated product-term architecture supporting sum-of-products implementation typical of the Classic era.
Typical applications for the EP910LI-20 include state-machine control, address decoding, glue logic replacement, and legacy system maintenance where modern FPGAs are unsuitable for form-factor or environmental reasons. The windowed ceramic DIP package supports field erasure via UV light, enabling iterative development cycles. The industrial temperature grade ('I' suffix) supports operation across -40C to +85C ambient environments.
When designing with this EPLD, designers must respect the 5V VCC requirement and the 20 ns propagation delay budget. Power sequencing should ensure clean rise/fall on VCC to avoid latch-up. For new designs, the EP910LC series in plastic DIP packages is recommended; the EP910LI is preferred for long-lifecycle, harsh-environment, or field-reprogrammable applications.
Drop-in alternatives for EP910LI-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LI-20 (same form factor and footprint) — differing in Package, Supply Voltage (VCC), Programming Method, Technology, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910LI-15
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$10.7 / Unit
View Datasheet →EP910LI-25
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EP910IPC-25
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$10.4 / Unit
View Datasheet →EP910IPC-15
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.95 / Unit
View Datasheet →EP910IPC-50
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$13.85 / Unit
View Datasheet →EP910IPC-12
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$14.2 / Unit
View Datasheet →EP910LI-20 Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Macrocells | 24 |
| Maximum Operating Frequency | 62 MHz |
| Propagation Delay (tpd) | 20 ns |
| Dedicated Inputs | 16 |
| I/O Pins | 24 |
| Supply Voltage (VCC) | 5 V |
| Operating Temperature | -40C to +85C (Industrial) |
| Package | 40-pin Ceramic DIP (Windowed) |
| Technology | CMOS, UV-erasable |
| Package Type | Through-Hole, Ceramic DIP with Quartz Window |
| Temperature Grade | Industrial (-40C to +85C) |
| Pin Count | 40 |
| Logic Family | EPLD (Erasable PLD) |
| Architecture | Sum-of-products macrocell |
| Pin/Package Compatibility | Pin-compatible across EP910 family |
EP910LI-20 Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin |
| Pin 2 | I/O — Bidirectional I/O pin |
| Pin 3 | I/O — Bidirectional I/O pin |
| Pin 4 | I/O — Bidirectional I/O pin |
| Pin 5 | I/O — Bidirectional I/O pin |
| Pin 6 | I/O — Bidirectional I/O pin |
| Pin 7 | I/O — Bidirectional I/O pin |
| Pin 8 | I/O — Bidirectional I/O pin |
| Pin 9 | GND — Ground reference |
| Pin 10 | I/O — Bidirectional I/O pin |
| Pin 11 | I/O — Bidirectional I/O pin |
| Pin 12 | I/O — Bidirectional I/O pin |
| Pin 13 | I/O — Bidirectional I/O pin |
| Pin 14 | I/O — Bidirectional I/O pin |
| Pin 15 | I/O — Bidirectional I/O pin |
| Pin 16 | I/O — Bidirectional I/O pin |
| Pin 17 | INPUT — Dedicated input pin |
| Pin 18 | INPUT — Dedicated input pin |
| Pin 19 | INPUT — Dedicated input pin |
| Pin 20 | GND — Ground reference |
| Pin 21 | INPUT — Dedicated input pin |
| Pin 22 | INPUT — Dedicated input pin |
| Pin 23 | INPUT — Dedicated input pin |
| Pin 24 | INPUT — Dedicated input pin |
| Pin 25 | INPUT — Dedicated input pin |
| Pin 26 | INPUT — Dedicated input pin |
| Pin 27 | INPUT — Dedicated input pin |
| Pin 28 | INPUT — Dedicated input pin |
| Pin 29 | INPUT — Dedicated input pin |
| Pin 30 | INPUT — Dedicated input pin |
| Pin 31 | INPUT — Dedicated input pin |
| Pin 32 | INPUT — Dedicated input pin |
| Pin 33 | I/O — Bidirectional I/O pin |
| Pin 34 | I/O — Bidirectional I/O pin |
| Pin 35 | I/O — Bidirectional I/O pin |
| Pin 36 | I/O — Bidirectional I/O pin |
| Pin 37 | I/O — Bidirectional I/O pin |
| Pin 38 | I/O — Bidirectional I/O pin |
| Pin 39 | I/O — Bidirectional I/O pin |
| Pin 40 | VCC — 5V supply voltage |
Typical Applications
EP910LI-20 is suitable for 6 applications: Industrial State-Machine Control, Address Decoding and Glue Logic, Legacy Avionics and Military Systems, VMEbus and Multibus Adapter Cards, Telecommunications Backplane Control, Test and Measurement Equipment.
Industrial State-Machine Control
The EP910LI-20's 24 macrocells provide ample capacity for medium-complexity state machines controlling legacy industrial machinery. With 20 ns propagation delay and 62 MHz toggle frequency, it can sequence stepper motors, conveyor interlocks, and sensor multiplexing at typical industrial cycle times of 1-10 ms. The ceramic windowed package supports field reprogramming via UV erasure, ideal for factory-floor firmware updates on equipment with multi-decade service lifetimes. Operating from -40C to +85C industrial temperature grade ensures reliability in unconditioned factory environments.
Recommended
Address Decoding and Glue Logic
The EP910LI-20 excels at replacing discrete 74-series glue logic and address-decoding PLAs in legacy CPU and memory subsystems. With 16 dedicated inputs and 24 I/O pins, it can decode full 24-bit address buses and generate chip-selects, DTACK, and bus-arbitration signals at 20 ns propagation delay. The 5V VCC operation matches vintage 8086, 68000, and VMEbus architectures. The macrocell-based architecture allows each output to be combinatorial or registered, replacing multiple discrete decoders with one integrated package.
Recommended
Legacy Avionics and Military Systems
The EP910LI-20 ceramic DIP package with UV window was widely deployed in 1990s avionics, radar signal processing, and military communications where field reprogrammability and extended temperature operation were critical. With industrial temperature grade and CMOS low-power architecture (~200 mA ICC), it remains in service on equipment such as flight-control test fixtures, legacy radar I/O interfaces, and military radio baseband processors. Per the verified web data, Rochester Electronics and authorized distributors continue to support long-term availability for these mission-critical platforms.
Recommended
VMEbus and Multibus Adapter Cards
The EP910LI-20 was a workhorse for VMEbus, Multibus, and STD-bus adapter card designs where bus-arbitration, interrupt-handling, and address-mapping logic needed to fit in a single socketed package. With 24 macrocells and 20 ns propagation delay, it can implement full VMEbus arbiter, interrupt-acknowledge sequencer, and address-decoder functions. The 40-pin ceramic DIP footprint is mechanically compatible with through-hole card cages common in industrial PLCs and rack-mounted controllers. Designers upgrading legacy systems can drop in faster or slower EP910 speed grades without PCB rework.
Recommended
Telecommunications Backplane Control
The EP910LI-20 is used in telecommunications backplane controllers for T1/E1 line-interface cards, where it performs alarm processing, line-coding translation, and test-loopback control. The 24 macrocells handle multiple independent control channels, while the 20 ns tpd supports real-time alarm response. The 5V CMOS technology matches telecom-card supply rails, and the ceramic windowed package enables field firmware updates during service interruptions. Legacy central-office switching platforms continue to deploy EP910 variants.
Recommended
Test and Measurement Equipment
The EP910LI-20 functions as the sequencer/controller in legacy test-and-measurement instruments such as oscilloscope trigger logic, spectrum-analyzer front-end control, and automated test-equipment (ATE) pin drivers. With 24 macrocells providing configurable registered or combinatorial outputs, it generates precise timing sequences for stimulus-response testing. The 20 ns propagation delay supports 50 MHz pattern generation, while the UV-erasable window allows engineers to iteratively refine test patterns during development without replacing the device.
Recommended
Recommended Products Summary
Engineering reference data for EP910LI-20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LI-15 | EP910LI-25 | EP910IPC-25 | EP910IPC-15 | EP910IPC-50 | EP910IPC-12 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera - same | Altera - same | Altera - same | Altera - same | Altera - same | Altera - same |
| Package | 40-pin Ceramic DIP (Windowed) | 40-pin Ceramic DIP (Windowed) - same | 40-pin Ceramic DIP (Windowed) - same | 40-pin Ceramic DIP (Windowed) - same | 40-pin Ceramic DIP (Windowed) - same | 40-pin Ceramic DIP (Windowed) - same | 40-pin Ceramic DIP (Windowed) - same |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tpd) | 20 ns | 15 ns | 25 ns | 25 ns | 15 ns | 50 ns | 12 ns |
| Toggle Frequency | 62 MHz | Higher (estimated 83 MHz) | Lower (estimated 50 MHz) | Lower (estimated 50 MHz) | Higher (estimated 83 MHz) | Lower (estimated 25 MHz) | Higher (estimated 100 MHz) |
| Supply Voltage (VCC) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| UV-Erasable Window | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Balanced 20 ns speed grade within the EP910 family (vs EP910LI-15)
- Industrial temperature grade in a windowed ceramic package (vs EP910LC-30)
- Faster speed grade available in same package (vs EP910LI-25)
Design Notes
The EP910LI-20 operates from a single 5V +/- 10% VCC supply per the Altera Classic EPLD family datasheet. Decouple VCC (pin 40) and GND (pins 9, 20) with a 0.1 uF ceramic capacitor placed within 5 mm of the package leads, plus a bulk 10 uF tantalum or electrolytic capacitor on the supply rail. Power sequencing should ensure VCC rises monotonically with a rise time of less than 50 ms to avoid CMOS latch-up. Typical ICC is approximately 200 mA during DC operation; transient current spikes during simultaneous output switching may exceed this and require adequate power-rail bulk capacitance.
For 40-pin ceramic DIP (Windowed) packages, route signal traces on the top signal layer with the IC socketed in a through-hole DIP pattern. Keep high-speed output traces short (< 50 mm) to limit ringing on the 20 ns-edge-rate outputs. Place a ground plane on the layer immediately below the signal layer to provide a low-impedance return path. The UV window faces upward; ensure no PCB component shadows the window during field erasure. Use a low-profile IC socket (e.g., Mill-Max 110-13-40) for easy device replacement during development.
Common pitfalls when designing with the EP910LI-20 include: (1) exceeding the 5V absolute-maximum VCC rating, which destroys the CMOS EPROM cells; (2) treating unused I/O pins as floating - per the datasheet, unused I/O must be set as outputs driving low or three-stated with a defined pull; (3) assuming pin compatibility with later MAX-series CPLDs - the EP910 pinout is unique to the Classic family; (4) programming with modern Altera/Intel Quartus software - the EP910 requires legacy APLUS or MAX+PLUS II software for JEDEC file generation. Field erasure requires 30-45 minutes of UV exposure at 254 nm wavelength with intensity > 15,000 uW/cm^2.
Compliance Information
RoHS and REACH compliance status is not published for the obsolete Altera Classic EPLD family. The ceramic DIP package contains a quartz window and may contain materials incompatible with modern RoHS thresholds; legacy exemption typically applies. Engineers should consult Rochester Electronics for current compliance documentation.
