EP910LI-30 - 24-Macrocell EPLD, 30ns, PQCC44 | Rochester/Altera
MPN: EP910LI-30 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $107.66 | $107.66 |
| 10 | $96 | $960.00 |
| 100 | $78 | $7,800.00 |
| 500 | $62 | $31,000.00 |
| 1,000 | $49.5 | $49,500.00 |
EP910LI-30 Overview
An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that sits in the design hierarchy between simple PLDs (PAL/GAL) and modern FPGAs/CPLDs. EPLDs use a sum-of-products AND/OR architecture with a programmable interconnect network and can be erased via ultraviolet light and re-programmed, making them ideal for prototyping and field updates. The EP910 occupies the mid-density tier of the Altera Classic family, providing more logic capacity than 22V10-style PALs while consuming far less board area than a discrete TTL/CMOS implementation.
Key features of the EP910LI-30 include 24 macrocells, 10 dedicated input pins and 22 I/O pins, 450 equivalent gates, 30ns pin-to-pin propagation delay (tPD), and a 5V ±5% single supply. The 'L' suffix denotes the low-power CMOS process, and the 'I' suffix indicates the industrial operating temperature range of -40C to +85C. The PQCC44 J-leaded package supports standard surface-mount assembly and is socket-compatible with the EP910LC44 (commercial-temperature variant), simplifying qualification across product lines.
Architecturally, the EP910 is implemented in 1.0-micron CMOS EPLD technology with EPROM-style programmable interconnect, providing non-volatile configuration retention without external configuration memory. Each macrocell contains a programmable flip-flop, feedback path, and output enable control. The device is programmed via a standard Altera/Altera-compatible programming algorithm and is fully supported by legacy MAX+PLUS II and classic Altera development toolchains.
Typical applications include TTL/CMOS glue-logic integration, address decoding for legacy 8-bit and 16-bit microprocessors (8086, 68000, Z80, 8051), bus-interface state machines, peripheral controllers, and replacement of discrete 74LS/74HC logic on industrial control boards. Its 30ns tPD suits buses clocked up to approximately 16 MHz. As of 2026-09-10 the part is supplied exclusively through authorized and aftermarket channels stocking Rochester Electronics inventory, reflecting original Altera EOL of the EP910 family in the late 1990s.
When designing with the EP910LI-30, allocate a 1.5 square-inch copper pour beneath the PLCC socket to keep junction temperature within industrial limits, and observe Altera's recommended programming algorithm for in-system or socket programming. Designers should also note that newer MAX II / MAX V CPLDs from Intel (formerly Altera) are NOT pin-compatible with the EP910 footprint.
This page synthesizes distributor pricing, Rochester Electronics lifecycle status, drop-in alternatives, and practical design notes not consolidated in the original Altera datasheet.
Drop-in alternatives for EP910LI-30 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LI-30 (same form factor and footprint) — differing in Supply Voltage (VCC), Package, Propagation Delay (tPD), Technology, Programming Method.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910LC-30
✅ Drop-In✓ In Stock
$22.5 / Unit
View Datasheet →EP910LC44-30T
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$9.75 / Unit
View Datasheet →EP910LC-30T
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.1 / Unit
View Datasheet →EP910LC44-30T
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$9.75 / Unit
View Datasheet →EP910LI-20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$19.95 / Unit
View Datasheet →EP910LC-25
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$2.2 / Unit
View Datasheet →EP910LI-30 Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD EP910 |
| Device Type | Erasable Programmable Logic Device (EPLD) |
| Macrocells | 24 |
| Equivalent Gates | 450 |
| Propagation Delay (tPD) | 30 ns |
| Supply Voltage (VCC) | 5 V ±5% (4.75 V to 5.25 V) |
| Operating Temperature | -40C to +85C (Industrial) |
| Process Technology | CMOS EPROM, UV-erasable |
| Package | 44-pin PQCC / PLCC-44 (J-lead) |
| Mounting Type | Surface Mount (socket recommended for UV erasure) |
| Dedicated Inputs | 10 |
| I/O Pins | 22 |
| Programming Method | Altera EPLD programming algorithm / MAX+PLUS II legacy support |
| Manufacturer (Original) | Altera (now Intel PSG) |
| Current Stocking Channel | Rochester Electronics (authorized aftermarket) |
EP910LI-30 Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin |
| Pin 2 | I/O — Bidirectional I/O pin |
| Pin 3 | I/O — Bidirectional I/O pin |
| Pin 4 | I/O — Bidirectional I/O pin |
| Pin 5 | I/O — Bidirectional I/O pin |
| Pin 6 | I/O — Bidirectional I/O pin |
| Pin 7 | GND — Ground |
| Pin 8 | I/O — Bidirectional I/O pin |
| Pin 9 | I/O — Bidirectional I/O pin |
| Pin 10 | I/O — Bidirectional I/O pin |
| Pin 11 | I/O — Bidirectional I/O pin |
| Pin 12 | I/O — Bidirectional I/O pin |
| Pin 13 | I/O — Bidirectional I/O pin |
| Pin 14 | INPUT — Dedicated input |
| Pin 15 | INPUT — Dedicated input |
| Pin 16 | INPUT — Dedicated input |
| Pin 17 | INPUT — Dedicated input |
| Pin 18 | INPUT — Dedicated input |
| Pin 19 | INPUT — Dedicated input |
| Pin 20 | INPUT — Dedicated input |
| Pin 21 | INPUT — Dedicated input |
| Pin 22 | INPUT — Dedicated input |
| Pin 23 | I/O — Bidirectional I/O pin |
| Pin 24 | I/O — Bidirectional I/O pin |
| Pin 25 | VCC — +5V supply |
| Pin 26 | I/O — Bidirectional I/O pin |
| Pin 27 | I/O — Bidirectional I/O pin |
| Pin 28 | I/O — Bidirectional I/O pin |
| Pin 29 | I/O — Bidirectional I/O pin |
| Pin 30 | I/O — Bidirectional I/O pin |
| Pin 31 | GND — Ground |
| Pin 32 | I/O — Bidirectional I/O pin |
| Pin 33 | I/O — Bidirectional I/O pin |
| Pin 34 | I/O — Bidirectional I/O pin |
| Pin 35 | I/O — Bidirectional I/O pin |
| Pin 36 | I/O — Bidirectional I/O pin |
| Pin 37 | I/O — Bidirectional I/O pin |
| Pin 38 | I/O — Bidirectional I/O pin |
| Pin 39 | I/O — Bidirectional I/O pin |
| Pin 40 | I/O — Bidirectional I/O pin |
| Pin 41 | I/O — Bidirectional I/O pin |
| Pin 42 | I/O — Bidirectional I/O pin |
| Pin 43 | INPUT — Dedicated input |
| Pin 44 | VCC — +5V supply |
Typical Applications
EP910LI-30 is suitable for 6 applications: Legacy Microprocessor Address Decoding, Bus-Interface State Machine, TTL/CMOS Glue-Logic Consolidation, Peripheral Controller Logic, Industrial Control Board Repair and Sustainment, Educational and Prototyping Platform.
Legacy Microprocessor Address Decoding
The EP910LI-30 is well-suited for address-decoding logic on legacy 8/16-bit microprocessor boards (8086, 68000, Z80, 8051) where its 24 macrocells and 30ns tPD cleanly replace multi-chip 74LS138/74LS139 decoder trees. The 30ns propagation delay sits comfortably below the address-to-DS setup window of 8 MHz 8086 and 12 MHz 68000 systems, while the 5V supply matches TTL rails without level shifting. With 10 dedicated inputs the device can decode up to 10 chip-select lines per macrocell array. Designers integrate the EP910LI-30 between the CPU address bus and peripheral chip-enable pins, replacing 4-6 discrete decoder packages with one PLCC-44 part and reducing board area by roughly 60 percent on legacy industrial-control motherboards.
Recommended
Bus-Interface State Machine
On ISA, STD, or VME peripheral cards the EP910LI-30 implements compact bus-arbitration and handshaking state machines that would otherwise consume 6-8 PALs or a discrete 74LS/74HC glue-logic array. The 24 macrocells provide enough flip-flops for 8-12 states, while the 30ns tPD satisfies ISA bus cycles (8 MHz) and STD-bus timing without wait states. The 5V supply aligns with classic peripheral buses, and the industrial -40 to +85C temperature range supports factory-floor deployment. Typical implementations replace 4 PAL22V10s and assorted MSI glue with one EP910LI-30, simplifying PCB layout and reducing power consumption by approximately 30 percent versus bipolar PAL equivalents.
Recommended
TTL/CMOS Glue-Logic Consolidation
The EP910LI-30 consolidates 8 to 15 SSI/MSI 74LS or 74HC packages into a single PLCC-44 EPLD, freeing board area and reducing assembly cost on legacy industrial controllers. The 450-gate equivalent capacity covers the typical 'one-board glue' workload of latches, muxes, encoders, and small counters found in motor drives, PLC backplanes, and CNC interfaces. Its 30ns propagation delay matches 74LS speed, while 5V single-supply operation eliminates the level shifters that 3.3V CPLDs would require on legacy 5V boards. Engineers commonly migrate designs by recoding the original discrete-logic equations into Altera AHDL or PAL-style CUPL, then programming the EP910LI-30 via MAX+PLUS II legacy toolchains still supported on Rochester-supplied silicon.
Recommended
Peripheral Controller Logic
The EP910LI-30 implements custom peripheral controllers (parallel-port bit-bangers, UART glue, IDE-interface state machines) on industrial embedded boards that still depend on the Classic EPLD silicon. The 24 macrocells accommodate the FIFOs, handshaking registers, and timing logic typical of legacy peripheral glue, while the 30ns tPD suits serial-port baud-rate generators up to 1 Mbaud. Designers pair the EP910LI-30 with a microprocessor host, using its 22 I/O pins to drive peripheral data buses and its 10 dedicated inputs to latch chip-select and interrupt lines. The industrial temperature range supports deployment in factory automation, building controls, and military/aerospace retrofit programs that require long-lifecycle silicon with documented pedigree.
Recommended
Industrial Control Board Repair and Sustainment
Field service and sustainment programs for legacy PLCs, CNC controllers, and factory-automation boards depend on the EP910LI-30 because the original Altera silicon is no longer in production. Rochester Electronics re-stocks this part from its authorized wafer/die bank, providing form-fit-function continuity for boards that cannot be redesigned without re-qualification. The 30ns tPD, 5V supply, PLCC-44 footprint, and -40 to +85C industrial temperature range match the original 1990s design intent exactly. Sustaining-engineering teams use the EP910LI-30 to repair boards whose original EP910 EPLDs have failed or were damaged by firmware bugs, without having to re-spinoff new CPLDs onto boards whose mechanical layout, certification, and safety approvals depend on the original EPLD footprint.
Recommended
Educational and Prototyping Platform
The EP910LI-30 remains in use on university digital-logic and computer-architecture labs because it teaches Classic EPLD architecture (AND/OR arrays, macrocell feedback, UV erasure) without the abstraction layers of modern FPGA toolchains. The 30ns speed grade is slow enough that students can probe macrocell outputs on a logic analyzer, yet fast enough to implement realistic glue-logic exercises at 1-5 MHz. The 5V supply matches benchtop power rails, and the PLCC-44 socket accepts UV-erasable parts for repeated lab cycles. Course materials reference MAX+PLUS II legacy software, which remains free for educational use. Universities pair the EP910LI-30 with breadboard-friendly breakout boards to expose all 44 pins to student exercises covering decoders, counters, and small RISC control units.
Recommended
Recommended Products Summary
Engineering reference data for EP910LI-30 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LC-30 | EP910LC44-30 | EP910LC-30T | EP910LC44-30T | EP910LI-20 | EP910LC-25 |
|---|---|---|---|---|---|---|---|
| Brand | Rochester Electronics (originally Altera) | Rochester Electronics (originally Altera) | Rochester Electronics (originally Altera) | Rochester Electronics (originally Altera) | Rochester Electronics (originally Altera) | Rochester Electronics (originally Altera) | Rochester Electronics (originally Altera) |
| Package | PLCC-44 (PQCC44) | PLCC-44 (PQCC44) - same | PLCC-44 (PQCC44) - same | PLCC-44 (PQCC44) - same | PLCC-44 (PQCC44) - same | PLCC-44 (PQCC44) - same | PLCC-44 (PQCC44) - same |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Equivalent Gates | 450 | 450 | 450 | 450 | 450 | 450 | 450 |
| Propagation Delay (tPD) | 30 ns | 30 ns | 30 ns | 30 ns | 30 ns | 20 ns (faster) | 25 ns (faster) |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) |
| Supply Voltage | 5V ±5% | 5V ±5% | 5V ±5% | 5V ±5% | 5V ±5% | 5V ±5% | 5V ±5% |
| Silicon Die | EP910 Classic EPLD | EP910 Classic EPLD - identical | EP910 Classic EPLD - identical | EP910 Classic EPLD - identical | EP910 Classic EPLD - identical | EP910 Classic EPLD - identical | EP910 Classic EPLD - identical |
| Lifecycle Status | EOL (1990s); Rochester active | EOL; Rochester active | EOL; Rochester active | EOL; Rochester active | EOL; Rochester active | EOL; Rochester active | EOL; Rochester active |
Key Differentiators
- Industrial temperature range qualification in original silicon (vs EP910LC-30)
- 30ns speed grade is the canonical baseline for EP910 family (vs EP910LI-20)
- Genuine authorized aftermarket silicon, not remarked parts (vs EP910IPC-25)
Design Notes
The EP910LI-30 is a CMOS EPLD with typical ICC active current in the tens of milliamperes and standby current under 1 mA. PLCC-44 has a theta_JA of approximately 60 C/W in still air on a standard 1 oz 4-layer board. For a 200 mW dissipation budget at 85C ambient, the junction temperature rise is about 12 C - well within the industrial 125C limit. Estimated: assume ICC active = 60 mA at 5V (300 mW worst case static), theta_JA = 60 C/W. No heatsink is required for the EP910LI-30 in typical PLCC-44 socket-mounted applications; however, ensure continuous airflow in fully enclosed industrial enclosures.
Mount the EP910LI-30 in a PLCC-44 through-hole socket (e.g. Aries 44-355 series or equivalent) rather than soldering directly to the PCB. A socket permits UV erasure for firmware rework, replacement of damaged parts without re-flow, and post-programming inspection under a quartz-window eraser. For designs that never require erasure, SMT is acceptable but verify the J-lead land pattern matches JEDEC PLCC-44 standard - third-party CAD libraries sometimes define PQCC44 land patterns incorrectly. Decouple VCC (pins 25 and 44) with a 0.1 uF ceramic capacitor placed within 3 mm of each pin, and add a single 10 uF tantalum bulk capacitor near the device.
Three common pitfalls when designing with the EP910LI-30: (1) the device requires a TTL-level 5V supply within 4.75V to 5.25V - operation below 4.75V violates timing guarantees and above 5.25V may damage the CMOS EPROM cells; (2) unused input pins MUST be tied to VCC or GND through a 10 kohm resistor - floating CMOS inputs draw excessive supply current and may oscillate; (3) when programming via legacy MAX+PLUS II, ensure the programming algorithm matches the EP910 device ID (0x08) - using the EP610 or EP1800 algorithm will fail to program correctly and may leave the device in an indeterminate state.
Compliance Information
RoHS / REACH / lead-free compliance not stated in scraped Rochester or DigiKey listings for the EP910LI-30. Original Altera EP910 family dates to pre-RoHS 1990s design; Rochester Electronics typically provides compliance statements on a per-lot basis. Contact Rochester technical support for the current lot's compliance documentation. AEC-Q100 not applicable - this is a logic device, not an automotive-qualified analog/interface IC. For automotive programs, consider whether the Industrial -40 to +85C rating suffices or whether a true AEC-Q100 part is required.
