EP910LI44 vs EP910LI-40 Comparison

Detailed side-by-side comparison of EP910LI44 by Altera and EP910LI-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910LI44 EP910LI-40
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.20 $12.90
Family Classic EPLD β€”
Architecture PAL-type, CMOS, One-Time-Programmable β€”
Macrocells 24 24
Package Type PLCC-44 (J-lead, surface mount) β€”
Total Pins 44 β€”
Dedicated Inputs 12 12
Bidirectional I/O 24 β€”
Maximum Logic Inputs 36 36
Maximum Outputs 24 β€”
Flip-Flops 24 β€”
External Clocks 2 β€”
Maximum Propagation Delay [DATA_NEEDED: tpd for unmarked speed grade; speed-grade suffix encodes value: -15 = 15 ns, -20 = 20 ns, -25 = 25 ns, -30 = 30 ns, -35 = 35 ns, -40 = 40 ns, -45 = 45 ns, -50 = 50 ns] β€”
Supply Voltage (VCC) 4.75 V to 5.25 V (commercial), 4.5 V to 5.5 V (industrial) β€”
Operating Temperature (L grade) -40 Β°C to +85 Β°C (industrial) β€”
Technology CMOS Low-power CMOS (L-suffix)
Programmability UV-erasable (windowed) or OTP UV-erasable, JEDEC-standard algorithm
RoHS Status non-compliant (original PLCC-44 lead finish) Non-compliant (windowed ceramic PLCC, legacy)
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount (socket-compatible)
Programming Method Altera Logic Programmer card / Data I/O / third-party EPROM programmers β€”
Manufacturer β€” Altera (now Intel PSG)
Product Family β€” Classic EPLD - EP910 series
Device Type β€” Erasable Programmable Logic Device (EPLD)
I/O Pins β€” 24 bidirectional
Product Terms β€” 240
Propagation Delay (tPD) β€” 40 ns
Operating Temperature β€” -40C to +85C (industrial, I-suffix)
Package β€” PLCC-44 (J-lead, windowed ceramic)
Lifecycle β€” Obsolete - replaced by MAX 7000 / MAX II CPLD family

Datasheets & Resources

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