EP910PC-15 vs EP910PC-30 Comparison
Detailed side-by-side comparison of EP910PC-15 by Altera and EP910PC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910PC-30
EP910PC-30 - 24-Macrocell Classic EPLD, 30ns, PDIP-40 | Altera
EP910PC-30 ObsoleteSpecification Comparison
| Parameter | EP910PC-15 | EP910PC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $12.80 | $6.50 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Usable Gates | 900 | ~450 |
| Macrocells | 24 | 24 |
| Maximum Pin-to-Pin Delay (tpd) | 15 ns | β |
| Counter Frequency (fCNT) | 100 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V Β±10% |
| Supply Current (Icc) | 80 mA typical | β |
| Dedicated Inputs | 10 | β |
| Dedicated I/O Pins | 12 | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Package | 24-pin PDIP (PDIP-24, 0.300 inch) | PDIP-40 (plastic DIP, 0.6 inch) |
| Mounting Type | Through-Hole | Through-hole DIP |
| Process Technology | CMOS, UV-erasable | β |
| Programming Method | Altera Logic Programmer card | β |
| RoHS Status | [DATA_NEEDED: RoHS status - EP910 is a legacy through-hole part, likely non-RoHS] | Non-compliant (contains lead, PDIP package) |
| MSL Level | Not applicable (through-hole) | β |
| Pin-to-Pin Propagation Delay (tPD) | β | 30 ns |
| Maximum Counter Frequency (fCNT) | β | 33.3 MHz |
| Logic Inputs | β | 36 dedicated |
| I/O Pins | β | 12 bidirectional |
| Logic Array Blocks (LABs) | β | 4 |
| Programming Technology | β | UV-erasable EPROM cell |
| TTL Emulation | β | 100% TTL-compatible |
| Power Dissipation | β | [DATA_NEEDED: power dissipation mW] |