EP910PC-15 - 900-Gate Classic EPLD, 15ns PDIP | Altera
MPN: EP910PC-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.2 | $28.20 |
| 10 | $22.5 | $225.00 |
| 100 | $18.75 | $1,875.00 |
| 500 | $15.4 | $7,700.00 |
| 1,000 | $12.8 | $12,800.00 |
EP910PC-15 Overview
An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of a PLA (programmable AND / fixed OR) with on-chip macrocells and a one-time- or UV-erasable CMOS process. In the system hierarchy, EPLDs sit between simple SPLDs/PALs and modern FPGAs, historically serving as glue-logic replacements that retain their configuration without a boot PROM. The Classic family is fabricated on advanced CMOS technology and supports 100% TTL emulation, making the EP910 a direct substitute for clusters of 20-pin and 24-pin PAL/GAL devices.
Key features of the EP910PC-15 include 24 macrocells, 10 dedicated input pins, 12 dedicated I/O pins, and a maximum toggle frequency of 100 MHz. The device operates from a single 5 V supply (VCC range 4.75 V to 5.25 V), draws Icc of typically 80 mA, and is packaged in a 24-pin, 0.300-inch-wide PDIP with through-hole leads. Programming is performed via the Altera Logic Programmer card on a standard PC parallel port.
Architecturally, the EP910 implements a sum-of-products PLA with a global interconnect and per-macrocell flip-flops with configurable D/T/JK/SR modes. Programmable output slew-rate control reduces ground bounce on heavily-loaded buses, and unused pins can be left open without damage - though the datasheet recommends enabling the internal pull-up resistor via the configuration bit.
Typical applications include TTL-logic replacement, address decoding for microprocessor systems, state-machine controllers, and bus-interface glue logic. Industrial control boards from the 1990s frequently use the EP910 as a peripheral decoder or interrupt controller. Because the part is in sustained production for legacy and long-lifecycle programs, it remains a popular choice for military, aerospace, and industrial sustainment designs.
When designing with the EP910PC-15, observe the 0.3-inch PDIP-24 footprint and provide a 0.1 uF decoupling capacitor adjacent to VCC. The device is obsolete on Altera's modern price book; long-term procurement should target franchised distributors holding date-code inventory rather than the open market.
Drop-in alternatives for EP910PC-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910PC-15 (same form factor and footprint) β differing in Package, Supply Voltage (VCC), Technology, Programming Method, Mounting Type.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP910PC-20
β Drop-Inβ In Stock
$12.4 / Unit
View Datasheet βEP910PC-25
β Drop-Inβ In Stock
$16.92 / Unit
View Datasheet βEP910PC-30
β Drop-Inβ In Stock
$6.5 / Unit
View Datasheet βEP910PC-35
β Drop-Inβ In Stock
$8.7 / Unit
View Datasheet βEP910PC-40
β Drop-Inπ Reference alternative (not in catalog)
EP610PC-15
β Drop-Inβ In Stock
$17.5 / Unit
View Datasheet βEP910PC-15 Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Usable Gates | 900 |
| Macrocells | 24 |
| Maximum Pin-to-Pin Delay (tpd) | 15 ns |
| Counter Frequency (fCNT) | 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Supply Current (Icc) | 80 mA typical |
| Dedicated Inputs | 10 |
| Dedicated I/O Pins | 12 |
| Operating Temperature | 0C to +70C (commercial) |
| Package | 24-pin PDIP (PDIP-24, 0.300 inch) |
| Mounting Type | Through-Hole |
| Process Technology | CMOS, UV-erasable |
| Programming Method | Altera Logic Programmer card |
| MSL Level | Not applicable (through-hole) |
EP910PC-15 Pin Configuration
| Pin 1 | I/O0 β Input/Output macrocell 0 |
| Pin 2 | I/O1 β Input/Output macrocell 1 |
| Pin 3 | I/O2 β Input/Output macrocell 2 |
| Pin 4 | I/O3 β Input/Output macrocell 3 |
| Pin 5 | I/O4 β Input/Output macrocell 4 |
| Pin 6 | I/O5 β Input/Output macrocell 5 |
| Pin 7 | I/O6 β Input/Output macrocell 6 |
| Pin 8 | I/O7 β Input/Output macrocell 7 |
| Pin 9 | I/O8 β Input/Output macrocell 8 |
| Pin 10 | I/O9 β Input/Output macrocell 9 |
| Pin 11 | I/O10 β Input/Output macrocell 10 |
| Pin 12 | I/O11 β Input/Output macrocell 11 |
| Pin 13 | IN0 β Dedicated input 0 |
| Pin 14 | IN1 β Dedicated input 1 |
| Pin 15 | IN2 β Dedicated input 2 |
| Pin 16 | IN3 β Dedicated input 3 |
| Pin 17 | IN4 β Dedicated input 4 |
| Pin 18 | IN5 β Dedicated input 5 |
| Pin 19 | IN6 β Dedicated input 6 |
| Pin 20 | IN7 β Dedicated input 7 |
| Pin 21 | IN8 β Dedicated input 8 |
| Pin 22 | IN9 β Dedicated input 9 |
| Pin 23 | GND β Ground |
| Pin 24 | VCC β +5 V supply |
Typical Applications
EP910PC-15 is suitable for 6 applications: TTL Logic Replacement, Microprocessor Address Decoding, State-Machine Controller, Bus-Interface Glue Logic, Legacy Industrial Control, Military and Aerospace Sustainment.
TTL Logic Replacement
The EP910PC-15 consolidates multiple 20-pin and 24-pin PAL/GAL devices into a single 24-pin PDIP part, simplifying board layout and reducing inventory. Its 100% TTL emulation means existing TTL designs can be re-implemented without changing input or output logic thresholds, and 15 ns tpd preserves the timing budget of the original discrete-logic implementation. This application was the original value proposition of the Altera Classic family and remains its strongest use case in legacy industrial control equipment.
Recommended
Microprocessor Address Decoding
The 24 macrocells of the EP910PC-15 provide enough product terms to decode the full 16-bit address bus of an 8086 or 68000 microprocessor plus several chip-select signals. With 15 ns tpd the decoder output settles within one clock cycle at 25 MHz, and the 5 V supply matches the legacy microprocessor rail. Industrial single-board computers and VMEbus controllers from the 1990s frequently used the EP910 in this role, and the part is still maintained in long-lifecycle defense and aerospace programs.
Recommended
State-Machine Controller
The Classic EPLD macrocell supports D, T, JK, and SR flip-flop modes with per-cell clock and reset, making the EP910PC-15 well suited for implementing state machines with up to 24 states. The 100 MHz internal counter frequency supports high-speed controllers such as UART bit-rate generators, quadrature decoders, and DMA handshakers. The non-volatile CMOS EEPROM configuration retains the state machine definition across power cycles without an external boot PROM, a key advantage over SRAM-based FPGAs of the same era.
Recommended
Bus-Interface Glue Logic
Bus-interface boards often need glue logic to align data, generate parity, or arbitrate between two masters - exactly the kind of mixed decode-and-register task the EP910PC-15 was designed for. Its 12 dedicated I/O pins drive 24 mA loads, sufficient for backplane buses such as ISA, STD, and VME, and the programmable output slew rate reduces ground bounce on heavily-loaded data buses. The PDIP-24 footprint suits through-hole backplane prototyping where SMT is not available.
Recommended
Legacy Industrial Control
The EP910 family is a workhorse in factory-floor PLCs, CNC controllers, and process-control equipment manufactured through the 1990s and 2000s. Equipment with a 20+ year service life - such as semiconductor fab tools, paper mills, and power-plant instrumentation - relies on the EP910PC-15 for sustainment spares. Its 0 to 70C commercial temperature range and PDIP package support through-hole repair by field technicians, a requirement in many industrial maintenance contracts that excludes SMT-only alternatives.
Recommended
Military and Aerospace Sustainment
Defense and aerospace platforms with multi-decade service lives - including avionics, naval combat systems, and ground-vehicle electronics - maintain EP910 inventory for sustainment. The part's documented availability through Altera's Classic EPLD long-term support program and its MIL-spec-compatible ceramic DIP variant (EP910DM/883B) keep it qualified for legacy military designs. Engineers replacing failed EP910PC-15 units must observe the original date-code and lot-trace requirements of their QPL/QML program.
Recommended
Recommended Products Summary
Engineering reference data for EP910PC-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910PC-20 | EP910PC-25 | EP910PC-30 | EP910PC-35 | EP910PC-40 | EP610PC-15 |
|---|---|---|---|---|---|---|---|
| Package | PDIP-24 | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Pin-to-Pin Delay (tpd) | 15 ns | 20 ns | 25 ns | 30 ns | 35 ns | 40 ns | 15 ns |
| Usable Gates | 900 | 900 | 900 | 900 | 900 | 900 | 600 |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 16 |
| Counter Frequency | 100 MHz | 100 MHz | 83.3 MHz | 62.5 MHz | 50 MHz | 40 MHz | 100 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C |
Key Differentiators
- 15 ns tpd is the fastest PDIP-24 grade in the EP910 family (vs EP910PC-20)
- Three times more usable gates than the smaller EP610 (vs EP610PC-15)
- Pin-compatible with slower speed grades for cost optimization (vs EP910PC-30)
Design Notes
The EP910PC-15 operates from a single 5 V supply with a typical Icc of 80 mA, meaning total power dissipation is approximately 400 mW in static operation and up to 600 mW with all outputs switching at 100 MHz. Provide at least one 0.1 uF ceramic decoupling capacitor adjacent to the VCC pin (pin 24) and a 10 uF bulk capacitor on the supply rail. The Classic family does not require power-supply sequencing beyond standard 5 V ramp-up.
The 24-pin PDIP footprint accepts a standard 0.300-inch-wide DIP socket or direct through-hole soldering on a 2.54 mm (0.100 inch) pitch. For prototyping, use a low-profile machine-pin socket to allow easy device removal and reprogramming. Keep input traces shorter than 50 mm to avoid transmission-line effects; the EP910 input thresholds are TTL-compatible (VIH = 2.0 V, VIL = 0.8 V) but the 15 ns edge rate can couple noise onto adjacent traces.
Do not assume the EP910PC-15 is RoHS-compliant - the part is a legacy through-hole device and most original date codes pre-date RoHS. Specify lead-free date codes explicitly when ordering for RoHS-compliant assemblies. The Altera Logic Programmer requires a PC parallel port (LPT1) which is no longer present on modern computers; plan for a USB-to-parallel adapter or a legacy programmer. Unused inputs should be tied to VCC through 10 kohm resistors to avoid floating-input oscillations.
Compliance Information
EP910PC-15 is a legacy through-hole PDIP part introduced before RoHS took effect. RoHS and lead-free status depend on date code; consult franchised distributor for current RoHS-compliant inventory. AEC-Q100 not applicable - automotive is not a target market for the Classic EPLD family.
