EP910PC-20T vs EP910PI-15T Comparison
Detailed side-by-side comparison of EP910PC-20T by Altera and EP910PI-15T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-20T | EP910PI-15T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Unknown | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.70 | $10.95 |
| Device Type | EPLD | β |
| Family | Classic EPLD | Altera Classic EPLD (EP910 series) |
| Fabrication Technology | CMOS | β |
| Logic Integration | 300 to 900 usable gates | β |
| Logic Emulation | 100% TTL emulation | β |
| Application Function | High-speed, low-power logic integration | β |
| Programmable Device Class | Erasable programmable logic device | β |
| Device Family | Altera Classic EPLD Family | β |
| Speed Grade | 20 ns | β |
| Package Code | PC | β |
| Package Pin Count | [DATA_NEEDED: package pin count] | β |
| Package Dimensions | [DATA_NEEDED: package dimensions] | β |
| Supply Voltage | [DATA_NEEDED: operating supply voltage] | 4.5 V to 5.5 V (5 V nominal) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial/commercial temp range] |
| I/O Count | [DATA_NEEDED: I/O count] | β |
| Internal Logic Capacity | 300 to 900 usable gates | β |
| Supported Logic Integration | Multiple PAL- and GAL-type devices | β |
| Programming Interface | [DATA_NEEDED: programming interface] | β |
| Programming Voltage | [DATA_NEEDED: programming voltage] | β |
| Mounting Technology | [DATA_NEEDED: mounting technology] | β |
| RoHS Status | unknown | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| REACH Status | unknown | β |
| AEC-Q100 Qualification | not_applicable | β |
| Lead-Free Status | unknown | β |
| Halogen-Free Status | unknown | β |
| Product Type | β | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | β | 24 |
| Dedicated Inputs | β | 12 |
| I/O Pins | β | 24 |
| Logic Blocks | β | 6 LABs of 4 macrocells each (Classic architecture) |
| Propagation Delay (tPD) | β | 15 ns max (speed grade -15) |
| Technology | β | CMOS EEPROM (electrically erasable) |
| Package | β | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| Mounting Type | β | Through-Hole |
| Output Drive Current | β | [DATA_NEEDED: per-pin DC output current, mA] |
| Programming | β | JEDEC-standard, serial/parallel programmer |