EP910PC-20T Classic EPLD | Altera | Logic Integration
MPN: EP910PC-20T β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.7 | $8.70 |
| 10 | $8.7 | $87.00 |
| 100 | $8.7 | $870.00 |
| 500 | $8.7 | $4,350.00 |
| 1,000 | $8.7 | $8,700.00 |
EP910PC-20T Overview
An EPLD is an erasable programmable logic device: an integrated circuit whose logic functions are configured by the user and can be erased and reprogrammed. EPLDs sit within the programmable logic hierarchy between simple PLDs and larger FPGA devices. They combine programmable AND/OR logic, fixed interconnect, and input/output blocks in a nonvolatile architecture, making them useful for replacing multiple discrete PAL and GAL devices. The Classic EPLD family provides a compact way to implement glue logic, registered state machines, decoders, counters, and interface conditioning in a single programmable component.
The EP910PC-20T is presented as a high-speed, low-power Classic EPLD. Its family-level positioning targets logic integration rather than the large sequential or signal-processing workloads commonly addressed by FPGAs. The supplied material states that the family supports 100% TTL emulation and that the EP910PC provides pin-to-pin logic integration for multiple PAL- and GAL-type devices. The 20 ns ordering suffix is treated as the device's specified speed grade, but a precise maximum operating frequency, propagation delay measurement condition, and power-consumption value are not available in the verified excerpts.
The CMOS fabrication process supports the family's low-power objective while providing the speed needed for conventional TTL-compatible digital logic. Unlike a fixed-function logic IC, the EP910PC-20T can be programmed for a particular board's decoding, control, or interface requirements. Unlike an FPGA, its smaller Classic EPLD architecture is generally associated with simpler logic integration and a more focused capacity range, although the supplied data does not state a direct comparison of internal resources.
Potential applications include legacy TTL logic consolidation, programmable address decoding, state-machine control, industrial control interfaces, and replacement of several PAL- or GAL-type devices on a board. The part is especially relevant to maintenance and redesign work involving existing Altera Classic EPLD designs, where changing the footprint or programming architecture may require board or firmware changes. Before new production use, verify the exact package drawing, supported programmer, software toolchain, and lifecycle status.
For design-in, confirm that the selected package, pinout, operating voltage, temperature range, timing grade, and programming procedure match the existing implementation. Do not infer electrical limits from the family description. Use the manufacturer datasheet and an approved programming workflow before relying on the part for a new design.
This page combines the verified EP910PC-20T search evidence, family-level application context, explicit missing-data markers, and replacement-screening guidance. It is intended to help engineers distinguish confirmed facts from parameters that require a full datasheet or device-specific cross-reference check.
Drop-in alternatives for EP910PC-20T β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910PC-20T (same form factor and footprint) β differing in Package, Supply Voltage (VCC), Programming Method, Speed Grade, Family.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP910PC-20
β Drop-Inβ In Stock
$12.4 / Unit
View Datasheet βEP910PC-15T
β Drop-Inβ In Stock
$14.2 / Unit
View Datasheet βEP910PC-15
β Drop-Inβ In Stock
$12.8 / Unit
View Datasheet βEP910PC-0
β Drop-Inβ In Stock
$8.7 / Unit
View Datasheet βEP610PC-20T
β Drop-Inβ In Stock
$7.2 / Unit
View Datasheet βEP910PC-20T Maximum Ratings & Electrical Characteristics
| Device Type | EPLD |
| Family | Classic EPLD |
| Fabrication Technology | CMOS |
| Logic Integration | 300 to 900 usable gates |
| Logic Emulation | 100% TTL emulation |
| Application Function | High-speed, low-power logic integration |
| Programmable Device Class | Erasable programmable logic device |
| Device Family | Altera Classic EPLD Family |
| Speed Grade | 20 ns |
| Package Code | PC |
| Internal Logic Capacity | 300 to 900 usable gates |
| Supported Logic Integration | Multiple PAL- and GAL-type devices |
| RoHS Status | unknown |
| REACH Status | unknown |
| AEC-Q100 Qualification | not_applicable |
| Lead-Free Status | unknown |
| Halogen-Free Status | unknown |
EP910PC-20T pc Pin Configuration Guide
Pin configuration for EP910PC-20T (pc package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP910PC-20T.
Refer to the datasheet for full pin configuration.
Typical Applications
EP910PC-20T is suitable for 6 applications: Legacy PAL and GAL Consolidation, TTL-Compatible Digital Control, Industrial Automation Logic, Programmable Address Decoding, State-Machine and Sequencing Control, Legacy Interface Conditioning.
Legacy PAL and GAL Consolidation
EP910PC-20T is suited to consolidating legacy PAL- and GAL-type logic into one Classic EPLD when a board-level redesign is already required. The verified family description specifically states that the EP910 family can integrate multiple PAL- and GAL-type devices, while the 20 ns ordering designation indicates a specified Classic EPLD speed grade. Before replacement, compare the original device equations, pin assignments, timing budget, and load conditions. The integrated approach can reduce component count and simplify inventory, but the exact logic capacity, package, and I/O count of EP910PC-20T are not supplied. Confirm the programming implementation and compare the full datasheets for every legacy device before releasing converted production artwork.
Recommended
TTL-Compatible Digital Control
EP910PC-20T can be considered for TTL-compatible control and interface logic because the verified Classic EPLD family material states 100% TTL emulation. Its CMOS construction and high-speed, low-power positioning support digital control, decoding, and registered logic tasks. The 20 ns ordering suffix is relevant to timing planning, but the supplied data does not define the exact propagation-delay test conditions, supply range, output current, or I/O limits. Use the device only after checking TTL input thresholds, output drive, fan-out, and timing against the system clock. A modern logic device may be preferable for new designs when a verified voltage range, current rating, and long-term availability are required.
Recommended
Industrial Automation Logic
EP910PC-20T may support industrial automation functions such as machine-state control, sensor-interface decoding, and deterministic glue logic. The verified data confirms CMOS fabrication, high-speed and low-power positioning, and Classic EPLD integration, but does not confirm an industrial temperature grade or current production status. Those omissions are material for factory equipment, where operating temperature, supply tolerance, reliability documentation, and lifecycle support must be established before design approval. The device can be useful for maintaining older automation electronics when the board already uses an Altera Classic EPLD and the required package and pinout are verified. For new industrial platforms, compare modern logic, CPLD, or FPGA options with documented temperature and longevity guarantees.
Recommended
Programmable Address Decoding
EP910PC-20T is a potential fit for programmable address decoding, chip-select generation, and memory-interface control where a Classic EPLD can replace several fixed logic devices. The family supports 100% TTL emulation and integrates multiple PAL- and GAL-type functions, which is useful when board logic must be consolidated without adopting a full FPGA development flow. The 20 ns speed grade requires a system-level timing review against the address and clock periods; the supplied excerpts do not provide a guaranteed maximum frequency or detailed timing model. Confirm package pinout, voltage levels, output drive, and decoder behavior in the complete datasheet. For high-speed modern memory interfaces, verify that the Classic EPLD timing is sufficient before relying on it in production.
Recommended
State-Machine and Sequencing Control
EP910PC-20T can implement state-machine, sequencing, and control functions in systems that need programmable logic without the resource scale of a large FPGA. The family description supports high-speed, low-power logic integration, while the 20 ns speed grade provides a basis for preliminary timing screening. However, the verified web material does not state the number of registers, macrocell count, maximum toggle frequency, or power consumption, so a new state-machine design cannot be fully budgeted from these excerpts alone. Confirm the logic resource, setup and hold requirements, clocking, and output loading in the manufacturer documentation. This application is most compelling for maintaining existing Classic EPLD platforms, repairing legacy boards, or consolidating proven PAL/GAL logic.
Recommended
Legacy Interface Conditioning
EP910PC-20T may be used to condition legacy digital interfaces, combine control signals, or adapt fixed board logic where multiple PAL/GAL devices are present. Its verified Classic EPLD positioning includes high-speed, low-power logic integration and support for 100% TTL emulation, making it a plausible candidate for existing TTL-based systems. The target device should not be selected from the family description alone: operating voltage, input thresholds, output drive, package, pinout, and programming compatibility remain unverified. For a new interface, compare the electrical constraints with the receiving logic and the physical board. For a legacy repair, preserve the original logic function, timing margin, and programming artifacts before changing the device or footprint.
Recommended
Recommended Products Summary
Engineering reference data for EP910PC-20T β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910PC-20 | EP910PC-15T | EP910PC-15 | EP910PC-0 | EP610PC-20T |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Device Family | Altera Classic EPLD Family | Altera Classic EPLD Family | Altera Classic EPLD Family | Altera Classic EPLD Family | Altera Classic EPLD Family | Altera Classic EPLD Family |
| Logic Integration | Multiple PAL- and GAL-type devices | EP910 family relationship; details unavailable | EP910 family relationship; details unavailable | EP910 family relationship; details unavailable | EP910 family relationship; details unavailable | EP610 family relationship; details unavailable |
| Drop-In Verification | Target device | Not verified; package, pinout, and timing comparison required | Not verified; package, pinout, and timing comparison required | Not verified; package, pinout, and timing comparison required | Not verified; package, pinout, and timing comparison required | Not verified; different family and no equivalence evidence |
Key Differentiators
- Classic EPLD family explicitly targets high-speed, low-power logic integration (vs EP610PC-20T)
- 20 ns ordering designation provides a documented speed-grade identifier (vs EP910PC-0)
- 100% TTL emulation is stated for the Classic EPLD family (vs EP910PC-15T)
- Integration of multiple PAL- and GAL-type devices (vs EP610PC-20T)
Design Notes
Do not treat the family description as a complete electrical specification. The verified data confirms CMOS technology, 100% TTL emulation, high-speed and low-power positioning, and a 20 ns ordering designation, but it does not provide supply voltage, output drive, I/O count, power consumption, or absolute maximum ratings. Before schematic release, obtain the manufacturer datasheet and check the recommended operating conditions, timing tables, programming requirements, and package drawing. This is especially important for legacy designs where an incorrect voltage or timing assumption can cause hidden functional failures.
Confirm the exact EP910PC-20T package and pin numbering before routing the PCB. The supplied evidence identifies the PC package code but does not state the package pin count, dimensions, or pin names. Do not borrow a pinout from EP910PC-20, EP910PC-15T, or another Classic EPLD. Compare the mechanical drawing and symbol against the selected ordering code, then verify every power, ground, clock, programming, and user-I/O connection. A package mismatch can invalidate an otherwise electrically reasonable design.
The 20 ns speed designation should be used for preliminary screening, not as a complete timing guarantee. The verified source does not state the delay test conditions, maximum clock rate, setup and hold times, or output-loading assumptions. For a new interface, calculate the required timing margin from the source clock, destination setup time, propagation delay, and board loading. For a legacy repair, preserve the original timing behavior and compare the replacement device under the same load and voltage conditions.
The supplied cross-reference results do not identify a verified drop-in substitute. Related parts such as EP910PC-20, EP910PC-15T, EP910PC-15, EP910PC-0, and EP610PC-20T appear in the site list, but the excerpts do not confirm identical packages, pinouts, logic capacity, programming, or electrical characteristics. Use these parts only for a documented engineering comparison. A same-family designation or similar ordering suffix is not sufficient evidence of drop-in compatibility.
Plan the board implementation around the verified use case of replacing multiple PAL- and GAL-type devices, but validate the target resource and I/O requirements first. The source states that the Classic EPLD family spans 300 to 900 usable gates, while EP910PC-20T-specific capacity is not supplied. Estimate equations, registers, macrocells, clock domains, and output loads from the original design, then confirm that the chosen Classic EPLD can implement them. For new hardware, compare the resulting resource and timing margin with a currently supported CPLD or FPGA alternative.
Compliance Information
The supplied verified web data does not state RoHS, REACH, lead-free, halogen-free, conflict-minerals, or AEC-Q100 status for EP910PC-20T. Compliance values are therefore unknown unless explicitly documented by the manufacturer.
