EP910PC-25 vs EP910DC-15 Comparison
Detailed side-by-side comparison of EP910PC-25 by Altera and EP910DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-25 | EP910DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.92 | $10.75 |
| Product Family | Classic EPLD | β |
| Usable Gates | 900 | β |
| Integration Gates (typical) | 4800 | β |
| Macrocells | 24 | 24 |
| Pin-to-Pin Delay (tPD) | 25 ns | β |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | β |
| Supply Voltage (VCC) | 5 V +/- 10% | 5 V (typical) |
| Technology | CMOS EPROM | CMOS EPROM, UV-erasable |
| Package | PDIP-24 (Plastic DIP) | 24-pin ceramic DIP (DC) |
| Pin Count | 24 | β |
| Dedicated Inputs | 10 | 12 |
| Dedicated I/O Pins | 12 | β |
| TTL Compatibility | 100% TTL emulation | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | Not erasable in plastic package (windowless) | β |
| Family | β | Altera Classic EPLD |
| Device Density | β | 900 usable gates |
| Logic Elements | β | [DATA_NEEDED: exact LE count] |
| Bidirectional I/O Pins | β | 12 |
| Flip-Flops | β | 10 |
| Product Terms per Macrocells | β | 24 |
| Maximum Propagation Delay (tPD) | β | 15 ns |
| Speed Grade | β | 15 |
| Mounting Type | β | Through-Hole |
| MSL Level | β | [DATA_NEEDED: MSL level] |
| RoHS Status | β | [DATA_NEEDED: not explicitly stated in verified data] |