EP910PC-30 vs EP910PC-25 Comparison
Detailed side-by-side comparison of EP910PC-30 by Altera and EP910PC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-30 | EP910PC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $6.50 | $16.92 |
| Family | Altera Classic EPLD | β |
| Macrocells | 24 | 24 |
| Usable Gates | ~450 | 900 |
| Pin-to-Pin Propagation Delay (tPD) | 30 ns | β |
| Maximum Counter Frequency (fCNT) | 33.3 MHz | β |
| Supply Voltage (VCC) | 5 V Β±10% | 5 V +/- 10% |
| Logic Inputs | 36 dedicated | β |
| I/O Pins | 12 bidirectional | β |
| Logic Array Blocks (LABs) | 4 | β |
| Package | PDIP-40 (plastic DIP, 0.6 inch) | PDIP-24 (Plastic DIP) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Technology | UV-erasable EPROM cell | β |
| TTL Emulation | 100% TTL-compatible | β |
| Power Dissipation | [DATA_NEEDED: power dissipation mW] | β |
| RoHS Status | Non-compliant (contains lead, PDIP package) | β |
| Mounting Type | Through-hole DIP | β |
| Product Family | β | Classic EPLD |
| Integration Gates (typical) | β | 4800 |
| Pin-to-Pin Delay (tPD) | β | 25 ns |
| Maximum Operating Frequency (fMAX) | β | 33.3 MHz |
| Technology | β | CMOS EPROM |
| Pin Count | β | 24 |
| Dedicated Inputs | β | 10 |
| Dedicated I/O Pins | β | 12 |
| TTL Compatibility | β | 100% TTL emulation |
| Erasure Method | β | Not erasable in plastic package (windowless) |