EP910PC30T vs EP910PC-20T Comparison
Detailed side-by-side comparison of EP910PC30T by Altera and EP910PC-20T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC30T | EP910PC-20T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Unknown |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.85 | $8.70 |
| Family | Altera Classic EPLD | Classic EPLD |
| Device Series | EP910 | β |
| Number of Macrocells | 24 | β |
| Number of I/O Pins | 24 | β |
| Number of Dedicated Inputs | 12 | β |
| Maximum Product Terms | 240 | β |
| Propagation Delay (tPD) | 30 ns | β |
| Maximum Clock Frequency (fMAX) | 33.3 MHz | β |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | β |
| Process Technology | CMOS | β |
| Programmable Logic Architecture | PAL-type sum-of-products, EPLD | β |
| Package | 24-pin PDIP (PC) | β |
| Mounting Type | Through-Hole (THT) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Speed Grade | -30 (30 ns tPD) | 20 ns |
| Programming Technology | EPROM (OTP in plastic package, UV-erasable in windowed package) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | unknown |
| Pin Count | 24 | β |
| Device Type | β | EPLD |
| Fabrication Technology | β | CMOS |
| Logic Integration | β | 300 to 900 usable gates |
| Logic Emulation | β | 100% TTL emulation |
| Application Function | β | High-speed, low-power logic integration |
| Programmable Device Class | β | Erasable programmable logic device |
| Device Family | β | Altera Classic EPLD Family |
| Package Code | β | PC |
| Package Pin Count | β | [DATA_NEEDED: package pin count] |
| Package Dimensions | β | [DATA_NEEDED: package dimensions] |
| Supply Voltage | β | [DATA_NEEDED: operating supply voltage] |
| I/O Count | β | [DATA_NEEDED: I/O count] |
| Internal Logic Capacity | β | 300 to 900 usable gates |
| Supported Logic Integration | β | Multiple PAL- and GAL-type devices |
| Programming Interface | β | [DATA_NEEDED: programming interface] |
| Programming Voltage | β | [DATA_NEEDED: programming voltage] |
| Mounting Technology | β | [DATA_NEEDED: mounting technology] |
| REACH Status | β | unknown |
| AEC-Q100 Qualification | β | not_applicable |
| Lead-Free Status | β | unknown |
| Halogen-Free Status | β | unknown |