EP910PC30T - 24 Macrocells CMOS Classic EPLD, 30ns DIP-24 | Altera
MPN: EP910PC30T ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $15.75 | $157.50 |
| 100 | $12.4 | $1,240.00 |
| 500 | $10.2 | $5,100.00 |
| 1,000 | $8.85 | $8,850.00 |
EP910PC30T Overview
A Classic EPLD (Erasable Programmable Logic Device) is a one-time- or UV-erasable PLD that preceded modern CPLDs and FPGAs in the programmable logic hierarchy. The taxonomy runs: programmable logic device (PLD) -> EPLD -> Classic EPLD -> complex PLD (CPLD), positioning the EP910 as a mid-density, low-power, deterministic-delay glue-logic IC that bridges the gap between simple PAL/GAL devices and modern CPLDs such as the MAX 7000 series.
Key specifications include 24 macrocells interconnected by a global programmable interconnect, 12 dedicated inputs, 24 I/O lines, up to 240 product terms, a maximum clock frequency of 33.3 MHz, and a propagation delay (tPD) of 30 ns. The device operates from a single 5V supply (typical VCC range 4.75 V to 5.25 V) and offers non-volatile, factory- or user-programmable AND/OR logic arrays.
Architecturally, the EP910PC30T uses a PAL-type sum-of-products macrocell structure with a global bus connecting all 24 macrocells, enabling deterministic 30 ns pin-to-pin delays regardless of routing path. The CMOS EPROM-based cell array provides zero standby power once programmed and supports a JEDEC-standard programming algorithm compatible with standard device programmers.
Typical applications include address decoding and bus-interface glue logic in 5V microprocessor systems, peripheral-chip replacement in legacy designs, state-machine and sequencer implementation, and industrial control logic where deterministic timing and 5V tolerance are required. The 30 ns speed grade makes it suitable for systems clocked up to 33 MHz.
When designing with the EP910PC30T, note that the part is non-erasable (one-time-programmable, OTP) in most package options; only ceramic-windowed packages permit UV erasure. Designers should also confirm 5V I/O compatibility with modern 3.3V logic, as the EP910 lacks 5V-tolerant inputs that would interface directly with low-voltage rails.
This page synthesizes distributor stock, same-package speed-grade alternatives, and practical design notes not found in the original 41-page Altera datasheet.
Drop-in alternatives for EP910PC30T — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910PC30T (same form factor and footprint) — differing in Package, Supply Voltage (VCC), Mounting Type, Technology, I/O Pins.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910PC-30
✅ Drop-In✓ In Stock
$6.5 / Unit
View Datasheet →EP910PC-35
✅ Drop-In✓ In Stock
$8.7 / Unit
View Datasheet →EP910PC-25
✅ Drop-In✓ In Stock
$16.92 / Unit
View Datasheet →EP910PC-20
✅ Drop-In✓ In Stock
$12.4 / Unit
View Datasheet →EP910PC-20T
✅ Drop-In✓ In Stock
$8.7 / Unit
View Datasheet →EP910PC/PI
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP910PC30T Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Device Series | EP910 |
| Number of Macrocells | 24 |
| Number of I/O Pins | 24 |
| Number of Dedicated Inputs | 12 |
| Maximum Product Terms | 240 |
| Propagation Delay (tPD) | 30 ns |
| Maximum Clock Frequency (fMAX) | 33.3 MHz |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) |
| Process Technology | CMOS |
| Programmable Logic Architecture | PAL-type sum-of-products, EPLD |
| Package | 24-pin PDIP (PC) |
| Mounting Type | Through-Hole (THT) |
| Speed Grade | -30 (30 ns tPD) |
| Programming Technology | EPROM (OTP in plastic package, UV-erasable in windowed package) |
| Pin Count | 24 |
EP910PC30T Pin Configuration
| Pin 1 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 2 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 3 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 4 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 5 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 6 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 7 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 8 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 9 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 10 | GND — Ground |
| Pin 11 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 12 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 13 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 14 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 15 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 16 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 17 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 18 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 19 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 20 | I/O — Macrocell I/O pin (bidirectional) |
| Pin 21 | INPUT — Dedicated input pin |
| Pin 22 | INPUT — Dedicated input pin |
| Pin 23 | INPUT — Dedicated input pin |
| Pin 24 | VCC — +5V power supply |
Typical Applications
EP910PC30T is suitable for 6 applications: 5V Microprocessor Address Decoding, Legacy Peripheral Chip Replacement, Industrial Control State Machines, VME / Multibus Address Mapping, Bus-Interface Glue Logic Consolidation, Legacy Test and Measurement Equipment.
5V Microprocessor Address Decoding
The EP910PC30T fits 5V microprocessor address decoding because its 24 macrocells and 240 product terms provide enough logic capacity to decode multi-chip-select address maps for 8-bit and 16-bit systems such as the 8086, 68k, and Z80 families. With a deterministic 30 ns pin-to-pin tPD, the device inserts well within one 33 MHz bus cycle, allowing chip-select generation without wait-states. Its 5V TTL-compatible I/O interfaces directly with classic peripheral ICs like the 8255 PPI, 8253 PIT, and 8237 DMA. Compared to discrete 74LS TTL decoder gates, the EP910PC30T replaces an entire board of glue logic in a single 24-pin PDIP, simplifying PCB layout and reducing the BOM in legacy industrial-control and instrumentation designs.
Recommended
Legacy Peripheral Chip Replacement
The EP910PC30T is well-suited to replacing obsolete or hard-to-source peripheral ICs because it can absorb the entire SSI/MSI logic function of a peripheral interface into a single 24-pin programmable part. Engineers migrating legacy PC/104, VME, or STD-bus designs can encode the original 74LS and 74F logic equations into JEDEC fuse maps, drop the EP910PC30T onto a 24-pin PDIP footprint, and ship a functionally identical board with a single supply chain. The 30 ns tPD matches classic NMOS/CMOS peripheral timing, ensuring software compatibility. Compared to modern CPLD replacements, the EP910PC30T's OTP EPROM technology and 5V-only operation avoid the JTAG and 3.3V issues that complicate drop-in upgrades on legacy boards.
Recommended
Industrial Control State Machines
The EP910PC30T's deterministic 30 ns tPD and 33.3 MHz fMAX make it a strong fit for industrial state machines where predictable timing matters more than raw throughput. With 24 macrocells, designers can implement 8 to 16-state FSMs with rich output decoding, supporting sequencing tasks such as conveyor control, packaging machinery, and process valve actuation. The 24-pin PDIP through-hole package withstands the vibration, thermal cycling, and rework service conditions common in factory-floor equipment, outperforming fine-pitch QFP packages in harsh environments. Compared to microcontrollers, the EP910PC30T offers sub-100 ns deterministic response with no firmware update risk - critical for safety interlocks and machinery directives requiring predictable shutdown behavior.
Recommended
VME / Multibus Address Mapping
The EP910PC30T suits VMEbus, Multibus, and STD-bus address-mapping applications because its 24 dedicated inputs accept the full 16- to 24-bit address bus plus control signals (AS, DS, R/W, DTACK), while its 24 outputs drive chip-select and DTACK generation logic. The 30 ns tPD fits comfortably within VME's 40 ns minimum bus-access timing, allowing the EP910PC30T to generate DTACK on-the-fly without inserting wait-states. The 5V CMOS I/O is fully compatible with VMEbus electrical specifications. Compared to discrete PROM- and PAL-based decode trees common in legacy VME designs, the EP910PC30T consolidates the entire address map into one reprogrammable device, simplifying board bring-up and field updates via JEDEC file reload.
Recommended
Bus-Interface Glue Logic Consolidation
The EP910PC30T consolidates SSI/MSI bus-interface glue logic because its 24 macrocells and 240 product terms replace dozens of 74LS00, 74LS138, and 74LS32 packages on a typical 5V CPU board. Designers can encode read/write strobe generation, address latch enable, chip-select decoding, and interrupt prioritization into a single 24-pin PDIP, freeing board area for higher-value functions. The 30 ns propagation delay matches the timing budget of 8 MHz to 25 MHz 5V microprocessors like the 8051, 68SEC000, and Z80. Compared to discrete TTL gates, the EP910PC30T reduces PCB trace congestion, lowers power consumption, and enables last-minute logic changes through JEDEC fuse-map updates - accelerating prototype iteration on legacy system revivals.
Recommended
Legacy Test and Measurement Equipment
The EP910PC30T serves in legacy test-and-measurement front-ends where 30 ns deterministic timing and 5V-only operation are mandatory for compatibility with analog front-end ASICs. Its 24 macrocells can implement counter prescalers, gate-array timing generators, and IEEE-488 (GPIB) handshake logic that older oscilloscopes, logic analyzers, and signal generators depend on. The through-hole PDIP package survives the thermal cycling of benchtop equipment and supports hand-soldering for field repairs. Compared to FPGAs, the EP910PC30T's zero-standby-power CMOS design avoids the inrush and configuration-power issues that complicate FPGA retrofitting in legacy instruments with tight 5V power budgets.
Recommended
Recommended Products Summary
Engineering reference data for EP910PC30T — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910PC-30 | EP910PC-35 | EP910PC-25 | EP910PC-20 | EP910PC-20T | EP910PC/PI |
|---|---|---|---|---|---|---|---|
| Package | PDIP-24 (PC) | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Number of Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Number of I/O Pins | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Supply Voltage | 5 V (4.75-5.25 V) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Programming Technology | OTP EPROM | OTP EPROM | OTP EPROM | OTP EPROM | OTP EPROM | OTP EPROM | OTP EPROM |
| Packaging Carrier | Tube (T&R suffix) | Tube (no T&R) | Tube | Tube | Tube | Tape & Reel | Tube |
Key Differentiators
- Balanced 30 ns speed grade suitable for 33 MHz 5V buses (vs EP910PC-35)
- Lower cost than faster speed grades while maintaining full 24-macrocell capacity (vs EP910PC-25 / EP910PC-20)
- Tape-and-Reel packaging for automated assembly versus tube-only siblings (vs EP910PC-30 (tube))
Design Notes
The EP910PC30T operates from a single 5V supply; per the Altera datasheet, the VCC pin (pin 24) should be decoupled with a 0.1 uF ceramic capacitor placed within 5 mm of the package pin, plus a 10 uF tantalum bulk capacitor on the same 5V rail. The CMOS EPROM architecture draws negligible standby current once programmed, but switching I/O simultaneously can produce transient current spikes of 20-40 mA per pin - design the 5V regulator to handle at least 200 mA peak headroom for a fully-loaded 24-output design.
The plastic PDIP EP910PC30T is one-time-programmable (OTP); once a JEDEC fuse map is committed, the device cannot be re-erased or re-programmed. For development, use the ceramic-windowed 'DC' or 'DM' variants to permit UV erasure, or use a modern MAX 7000S CPLD for ISP-capable prototyping. Additionally, the 5V CMOS I/O lacks 5V-tolerant inputs when interfacing to 3.3V logic - always insert a level shifter (e.g., 74HCT245) on the 3.3V-to-5V boundary to prevent input overstress and potential long-term reliability degradation.
The 24-pin PDIP through-hole footprint is robust for hand-soldering and field-repair but occupies significant board area versus modern QFP packages. When laying out the EP910PC30T on legacy 5V boards, route all 24 I/O traces on a single signal layer with ground reference, and place 4.7 kohm or 10 kohm pull-up resistors on unused I/O pins to prevent floating-input CMOS oscillations. Avoid placing the device near high-current switching nodes (relays, solenoids) without a guard ground trace - the EPROM technology is sensitive to latch-up from substrate-current transients exceeding the Absolute Maximum ratings.
Compliance Information
Operating temperature range, RoHS, REACH, lead-free, and halogen-free status are not stated in the Verified Web Data. Altera Classic EPLDs (1990s origin) were generally not RoHS-compliant in their original release; the PDIP-24 plastic package likely contains lead-based solder terminations. AEC-Q100 not applicable as Classic EPLDs are not automotive-qualified.
