EPC144LC-20 vs EPC1441LI20 Comparison
Detailed side-by-side comparison of EPC144LC-20 by Altera and EPC1441LI20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC144LC-20 | EPC1441LI20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.15 | $8.10 |
| Memory Type | OTP EPROM (One-Time Programmable) | OTP Configuration PROM (PROM) |
| Memory Size | 440,800 bits (440 kb) | β |
| Configuration Interface | Altera serial daisy-chain | Altera 4-pin serial (DATA, DCLK, nCONFIG, nSTATUS) |
| Access Time (Speed Grade) | 20 ns | β |
| Supply Voltage (VCC) | [DATA_NEEDED: VCC min/max] | β |
| Supply Voltage (VPP) | [DATA_NEEDED: VPP programming voltage] | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (industrial) |
| Package Type | 20-pin PLCC (J-lead) | β |
| Package Dimensions | 9 x 9 mm | β |
| Mounting Type | Surface Mount | β |
| Compatible FPGA Families | FLEX 10K, FLEX 8000, ACEX 1K | β |
| Programming Method | Altera Logic Programmer / JTAG | One-Time-Programmable via Altera programming hardware |
| Process Technology | CMOS | β |
| MSL Level | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Daisy-Chain Support | Yes (multiple PROMs cascadable) | β |
| Manufacturer | Altera (now Intel FPGA) | β |
| Density | β | 441 kbits (440,800 bits) |
| Number of Words | β | 440,800 |
| Bits per Word | β | 1 bit |
| Supported FPGA Families | β | ACEX, APEX 20K / 20KC / 20KE, FLEX 10KE, FLEX 10KA, Mercury |
| Supply Voltage | β | 3.3 V |
| Package | β | 20-pin PLCC (J-lead, 9x9 mm) |
| Pin Pitch | β | 1.27 mm |
| Configuration Time | β | Depends on FPGA bitstream length and DCLK frequency |