EPC144LC-20 - Altera OTP Configuration PROM | 20-PLCC
MPN: EPC144LC-20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.15 | $7,150.00 |
EPC144LC-20 Overview
A Configuration PROM is a type of non-volatile serial memory used to bootstrap programmable logic devices. In the hierarchy of programming technologies, the EPC144 belongs to the OTP EPROM family, sitting below modern flash-based PROMs and above discrete bitstream storage solutions. It functions as a small, low-density serial ROM that interfaces with an FPGA's configuration controller, presenting itself as a peripheral device that delivers configuration frames on demand during the FPGA's multi-stage boot sequence. The EPC144 family represents Altera's second-generation configuration architecture that preceded the flash-based EPCS and EPCQ families.
Key features of the EPC144LC-20 include 440,800 bits of OTP storage, a serial daisy-chain configuration interface, compatibility with FLEX 10K, FLEX 8000, and ACEX 1K FPGA families, low-power CMOS process technology, and a 20-pin PLCC package with a J-lead footprint. The -20 speed grade denotes a 20 ns access time, suitable for configuration of Altera FPGAs operating at configuration clock frequencies up to approximately 50 MHz.
The EPC144LC-20 uses a serial daisy-chain architecture allowing multiple PROMs to be cascaded for larger bitstreams. Programming is performed using the Altera Logic Programmer card or compatible third-party programmers via JTAG-like boundary-scan mechanisms. The device operates from a single 5V supply and offers standard CMOS input thresholds, making it directly compatible with 5V-tolerant FPGA configuration pins of legacy Altera devices.
Typical applications include legacy industrial control systems, telecom infrastructure retrofits, and defense/aerospace systems where the original Altera FLEX 10K or ACEX 1K FPGA designs must be maintained. Engineers designing new products should consider migrating to flash-based EPCQ or serial configuration devices from modern vendors, as the EPC144 family is no longer in active production.
When designing with the EPC144LC-20, ensure proper decoupling (0.1 uF ceramic capacitor near VCC) and verify that the FPGA's configuration mode pins select serial configuration mode. The OTP nature means that bitstreams cannot be erased or rewritten, so design verification must occur before programming.
This page synthesizes distributor availability, drop-in configuration PROM alternatives, and practical design considerations not found in a single manufacturer document.
Drop-in alternatives for EPC144LC-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC144LC-20 (same form factor and footprint) — differing in Memory Type, Programming Method, Operating Temperature, Package, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC1441LC20N
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EPC1441LC20
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Contact for price
View Datasheet →EPC1441LI20N
✅ Drop-In✓ In Stock
$4.29 / Unit
View Datasheet →EPC1441LI20
✅ Drop-In✓ In Stock
$8.1 / Unit
View Datasheet →EPC144LC20
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$7.1 / Unit
View Datasheet →EPC144L20
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$16.2 / Unit
View Datasheet →EPC144LC-20 Maximum Ratings & Electrical Characteristics
| Memory Type | OTP EPROM (One-Time Programmable) |
| Memory Size | 440,800 bits (440 kb) |
| Configuration Interface | Altera serial daisy-chain |
| Access Time (Speed Grade) | 20 ns |
| Package Type | 20-pin PLCC (J-lead) |
| Package Dimensions | 9 x 9 mm |
| Mounting Type | Surface Mount |
| Compatible FPGA Families | FLEX 10K, FLEX 8000, ACEX 1K |
| Programming Method | Altera Logic Programmer / JTAG |
| Process Technology | CMOS |
| Daisy-Chain Support | Yes (multiple PROMs cascadable) |
| Manufacturer | Altera (now Intel FPGA) |
EPC144LC-20 Pin Configuration
| Pin 1 | DATA — Serial data output to FPGA |
| Pin 2 | DCLK — Configuration clock input from FPGA |
| Pin 3 | VCC — +5V supply |
| Pin 4 | NC — Not connected |
| Pin 5 | nCS — Chip select (active low) |
| Pin 6 | NC — Not connected |
| Pin 7 | GND — Ground |
| Pin 8 | OE — Output enable |
| Pin 9 | NC — Not connected |
| Pin 10 | VPP — Programming voltage supply |
| Pin 11 | NC — Not connected |
| Pin 12 | NC — Not connected |
| Pin 13 | NC — Not connected |
| Pin 14 | NC — Not connected |
| Pin 15 | NC — Not connected |
| Pin 16 | NC — Not connected |
| Pin 17 | NC — Not connected |
| Pin 18 | NC — Not connected |
| Pin 19 | NC — Not connected |
| Pin 20 | GND — Ground |
Typical Applications
EPC144LC-20 is suitable for 6 applications: Legacy FLEX 10K FPGA Configuration, ACEX 1K FPGA Boot Storage, Telecom Infrastructure Retrofits, Industrial Control System Sustainment, Defense and Aerospace Legacy Sustainment, Prototype and Development Board Configuration.
Legacy FLEX 10K FPGA Configuration
The EPC144LC-20 was designed specifically as a configuration PROM for the Altera FLEX 10K family of FPGAs, providing non-volatile 440 kb storage for the device's configuration bitstream. At system power-up, the EPC144LC-20 serially transfers the stored bitstream into the FLEX 10K via Altera's serial configuration interface, eliminating the need for parallel boot ROMs. The 440 kb capacity covers FLEX 10K devices up to the EPF10K50, and multiple EPC144LC-20 devices can be daisy-chained to support larger FLEX 10K members. For new FLEX 10K retrofits, consider the flash-based EPC1441LC20N for field reprogrammability.
Recommended
ACEX 1K FPGA Boot Storage
The EPC144LC-20 serves as the configuration memory for Altera ACEX 1K FPGAs in legacy industrial systems. The 440 kb OTP storage is sufficient for most ACEX 1K bitstreams (EP1K50 and smaller), and the 20 ns access time keeps pace with the ACEX 1K serial configuration controller. The OTP nature of the EPC144LC-20 makes it appropriate for ACEX 1K designs that must lock the bitstream permanently at production. For designs requiring in-system updates, the EPC1441LC20N is the pin-compatible flash-based alternative that maintains the same PLCC-20 footprint.
Recommended
Telecom Infrastructure Retrofits
Legacy telecom switches, base-station controllers, and transmission equipment often rely on Altera FLEX 10K or FLEX 8000 FPGAs whose bitstreams were originally stored in EPC144 configuration PROMs. When these systems require repair or board-replacement, the EPC144LC-20 (or its flash-based successor EPC1441LC20N) provides the original configuration source. The PLCC-20 socketed package simplifies field replacement, and the OTP storage ensures bitstream authenticity for regulated telecom environments. Distributors specializing in obsolete components (FPGAkey, FindComponents) maintain EPC144LC-20 stock for this use case.
Recommended
Industrial Control System Sustainment
Long-lifecycle industrial automation systems (PLCs, motor drives, process controllers) built around Altera FLEX 8000 and ACEX 1K FPGAs require ongoing configuration PROM availability for sustainment over 15-25 year service windows. The EPC144LC-20, though obsolete in mainstream distribution, remains available through specialty brokers for these programs. The 20-pin PLCC package is socket-compatible, enabling hot-swap of failed configuration PROMs without reworking the base board. For new industrial control designs targeting similar longevity, the EPC1441LI20N (industrial temperature grade) is recommended.
Recommended
Defense and Aerospace Legacy Sustainment
Military and aerospace platforms with multi-decade service lives depend on Altera FLEX 10K and ACEX 1K FPGA-based subsystems whose bitstreams were stored in EPC144 OTP PROMs. The OTP behavior of the EPC144LC-20 is intentional in these applications - it prevents in-field bitstream modification, supporting anti-tamper requirements. Sustainment programs source EPC144LC-20 from qualified obsolete-part distributors that perform lot traceability and upscreening. New defense designs targeting equivalent behavior should specify the EPC1441LC20N with secure programming flow control.
Recommended
Prototype and Development Board Configuration
Altera FPGA development boards (legacy Altera DevKit and university lab boards) often include the EPC144LC-20 or compatible EPC1441 series PROMs to configure on-board FLEX 10K / ACEX 1K FPGAs. Students and engineers working with these legacy boards use the EPC144LC-20 to load custom bitstreams during prototyping. Although the OTP limitation requires a new PROM per design iteration, this matches the educational use case where each lab exercise builds a fresh configuration. Modern labs should migrate to EPC1441LC20N-equipped boards for repeated reprogramming.
Recommended
Recommended Products Summary
Engineering reference data for EPC144LC-20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC1441LC20N | EPC1441LC20 | EPC1441LI20N | EPC1441LI20 | EPC144LC20 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 20-pin PLCC (9x9 mm) | 20-pin PLCC (9x9 mm) - same | 20-pin PLCC (9x9 mm) - same | 20-pin PLCC (9x9 mm) - same | 20-pin PLCC (9x9 mm) - same | 20-pin PLCC (9x9 mm) - same |
| Memory Type | OTP EPROM | Flash (reprogrammable) | Flash (reprogrammable) | Flash (reprogrammable) | Flash (reprogrammable) | OTP EPROM |
| Memory Capacity | 440 kb (440,800 bits) | 440 kb | 440 kb | 440 kb | 440 kb | 440 kb |
| Configuration Interface | Altera serial daisy-chain | Altera serial daisy-chain | Altera serial daisy-chain | Altera serial daisy-chain | Altera serial daisy-chain | Altera serial daisy-chain |
| Access Time | 20 ns | 20 ns | 20 ns | 20 ns | 20 ns | 20 ns |
| Reprogrammable | No (OTP) | Yes (flash) | Yes (flash) | Yes (flash) | Yes (flash) | No (OTP) |
| Lifecycle Status | Obsolete | Obsolete (but available) | Obsolete (but available) | Obsolete (but available) | Obsolete (but available) | Obsolete |
| Compatible FPGA Families | FLEX 10K, FLEX 8000, ACEX 1K | FLEX 10K, FLEX 8000, ACEX 1K | FLEX 10K, FLEX 8000, ACEX 1K | FLEX 10K, FLEX 8000, ACEX 1K | FLEX 10K, FLEX 8000, ACEX 1K | FLEX 10K, FLEX 8000, ACEX 1K |
Key Differentiators
- OTP behavior for irreversible bitstream lock (vs EPC1441LC20N)
- Direct legacy compatibility with original Altera toolchain (vs EPC1441LC20N)
- Same PLCC-20 footprint as EPC1441 series (vs EPC1441LC20N)
Design Notes
The EPC144LC-20 is OTP (one-time programmable) - any programming error or design revision requires a new physical device. For development and prototyping, use the flash-based EPC1441LC20N instead, which allows repeated in-system reprogramming via JTAG. Reserving the OTP EPC144LC-20 for production-only builds prevents wasteful scrap during firmware iteration.
Place a 0.1 uF decoupling capacitor as close as possible to the VCC pin (pin 3) of the EPC144LC-20 to suppress supply noise during configuration clock edges. The serial configuration interface transitions at high speed during FPGA boot, and inadequate decoupling can cause data corruption on the DATA line. A bulk 10 uF tantalum or ceramic capacitor on the same 5V rail provides additional noise immunity for multi-PROM daisy-chain configurations.
Route the DCLK (pin 2) and DATA (pin 1) traces as a controlled-impedance differential pair with matched lengths, because skew between clock and data will cause FPGA configuration errors. Keep the trace length under 150 mm to minimize signal degradation. If multiple EPC144LC-20 devices are daisy-chained, add 22 ohm series-termination resistors at each PROM's DATA output to suppress ringing on the longer cumulative trace run.
Compliance Information
Compliance information not available in the verified web data. EPC144LC-20 is an obsolete part predating modern RoHS documentation standards; consult the manufacturer directly for compliance certificates if required for legacy sustainment.