EPC144LC20 vs EPC160C100 Comparison
Detailed side-by-side comparison of EPC144LC20 by Intel and EPC160C100 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC144LC20
EPC144LC20 - 144KB Serial Config PROM, 20-LCC | Intel (Altera)
EPC144LC20 β Last Time BuyAltera
EPC160C100
EPC160C100 - Altera Enhanced Configuration Device | Intel FPGA
EPC160C100 ObsoleteSpecification Comparison
| Parameter | EPC144LC20 | EPC160C100 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | Memory ICs |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $7.20 |
| Memory Capacity | 144 Kbit | β |
| Memory Organization | Serial (one-time programmable) | β |
| Interface Type | Altera Serial Configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | β |
| Programming Method | In-system via JTAG (IEEE 1149.1 / ByteBlaster / USB-Blaster) | β |
| Supply Voltage (VCC) | 3.0 V to 5.5 V | β |
| Operating Temperature | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Configuration Time (typical) | [DATA_NEEDED: configuration time at DCLK = 10 MHz] | β |
| Active Supply Current | [DATA_NEEDED: ICC active] | β |
| Standby Supply Current | [DATA_NEEDED: ICC standby] | β |
| Package | 20-pin LCC (Leadless Chip Carrier, JLCC-20) | PQFP-100 |
| Pin Count | 20 | 100 |
| Mounting Type | Surface Mount | Surface Mount |
| Supported FPGA Families | Altera FLEX 6000 / 8000 / 10K, ACEX 1K, MAX 3000 / 7000, APEX 20K | Altera APEX, Cyclone, Stratix, and other SRAM-based LUT devices |
| MSL Level | 3 (168 hours) | [DATA_NEEDED: MSL rating] |
| RoHS Status | [DATA_NEEDED: RoHS compliance status per Intel PCN] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | Yes | [DATA_NEEDED: lead-free status] |
| Halogen-Free | [DATA_NEEDED] | β |
| JTAG Compliance | IEEE Std 1149.1 | β |
| Device Type | β | Enhanced Configuration Device (EPC) for SRAM-based LUT FPGAs |
| Configuration Density | β | 160 Mbit equivalent tier |
| Operating Voltage (Core) | β | 3.3 V |
| Programming Interface | β | JTAG (IEEE 1149.1) in-system programmable |
| Configuration Interface | β | Serial / Parallel, Altera nCONFIG/nSTATUS/CONF_DONE protocol |
| Cascade Support | β | Yes (nCASC pin for multi-FPGA daisy chain) |
| Memory Technology | β | Flash-based non-volatile configuration memory |