EPC144LC20 - 144KB Serial Config PROM, 20-LCC | Intel (Altera)
MPN: EPC144LC20 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.1 | $7,100.00 |
EPC144LC20 Overview
An FPGA configuration PROM is a one-time or few-time programmable serial memory that holds the FPGA's bitstream. When the system powers up, the FPGA loads its logic configuration from the PROM through a synchronous serial link. The EPC144LC20 is part of Altera's classic EPC1 series configuration memories, designed to support legacy Altera FPGA families such as the FLEX 6000, FLEX 8000, FLEX 10K, ACEX 1K, MAX 7000, MAX 3000 and APEX 20K series. The PROM is organized as a serial shift register; an internal oscillator generates the configuration clock, simplifying host design.
Key features include 144 Kbit storage capacity, automatic continuous configuration on power-up, low-pin-count serial interface (4 signal pins plus VCC/GND), 3.3V or 5V operation, in-system programmable via IEEE Std 1532 / Jam STAPL, and a compact 20-pin LCC surface-mount footprint (also known as LCC-20 or JLCC-20). The device is one-time programmable (OTP) in standard configuration, simplifying bill-of-material by removing external programming steps at board build. Programming is performed via the JTAG-compatible 4-wire interface using Altera's Quartus II / MAX+PLUS II toolchains.
Typical applications include configuration memory for legacy Altera FPGAs, industrial controllers using FLEX 10K or APEX 20K devices, telecom line cards with MAX 7000 glue logic, retrofits of legacy Altera designs where original EPROM-based configuration is replaced by a single chip, and embedded systems that boot from a serial bitstream. The EPC144LC20 is also widely used in CPLD-based glue logic designs where a small FPGA is configured by an adjacent configuration PROM.
When designing with this device, place decoupling capacitors as close as possible to the VCC pins (typically one 0.1 uF ceramic per supply pin). The LCC-20 package has no exposed thermal pad; the device draws minimal current during configuration (typically <50 mA active, <100 uA standby) so no heatsink is required. Ensure the JTAG chain (TCK/TMS/TDO/TDI) is terminated correctly if multiple Altera devices share the chain; use Altera's ByteBlaster or USB-Blaster cables for in-system programming.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet. The EPC144LC20 is a legacy configuration device with mature second-source options; consult the Intel (Altera) Configuration Devices datasheet for full timing specifications.
Drop-in alternatives for EPC144LC20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC144LC20 (same form factor and footprint) β differing in Package, Memory Type, Configuration Interface, Mounting Type, Memory Size.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPC1441LC20
β Drop-Inβ In Stock
Contact for price
View Datasheet βEPC144LC20-3
β Drop-Inπ Reference alternative (not in catalog)
EPC144ILC20
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEPC144ICC20
β Drop-Inβ In Stock
$7.45 / Unit
View Datasheet βEPC1441-LC20
β Drop-Inβ In Stock
$1.05 / Unit
View Datasheet βEPC144LC20 Maximum Ratings & Electrical Characteristics
| Memory Capacity | 144 Kbit |
| Memory Organization | Serial (one-time programmable) |
| Interface Type | Altera Serial Configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Programming Method | In-system via JTAG (IEEE 1149.1 / ByteBlaster / USB-Blaster) |
| Supply Voltage (VCC) | 3.0 V to 5.5 V |
| Operating Temperature | -40C to +85C (industrial) |
| Package | 20-pin LCC (Leadless Chip Carrier, JLCC-20) |
| Pin Count | 20 |
| Mounting Type | Surface Mount |
| Supported FPGA Families | Altera FLEX 6000 / 8000 / 10K, ACEX 1K, MAX 3000 / 7000, APEX 20K |
| MSL Level | 3 (168 hours) |
| Lead-Free | Yes |
| JTAG Compliance | IEEE Std 1149.1 |
EPC144LC20 Pin Configuration
| Pin 1 | VCC β Power supply (3.0V to 5.5V) |
| Pin 2 | DATA β Serial configuration data output to FPGA |
| Pin 3 | DCLK β Configuration clock output to FPGA |
| Pin 4 | nCONFIG β Configuration control input from FPGA |
| Pin 5 | nSTATUS β Configuration status output to FPGA |
| Pin 6 | CONF_DONE β Configuration complete output |
| Pin 7 | TCK β JTAG test clock |
| Pin 8 | TMS β JTAG test mode select |
| Pin 9 | TDO β JTAG test data out |
| Pin 10 | TDI β JTAG test data in |
| Pin 11 | GND β Ground |
| Pin 12 | NC β Not connected (per datasheet) |
| Pin 13 | NC β Not connected (per datasheet) |
| Pin 14 | OE β Output enable / nCS, tie low for always-selected |
| Pin 15 | NC β Not connected (per datasheet) |
| Pin 16 | GND β Ground |
| Pin 17 | NC β Not connected (per datasheet) |
| Pin 18 | NC β Not connected (per datasheet) |
| Pin 19 | VCC β Power supply (3.0V to 5.5V) |
| Pin 20 | NC β Not connected (per datasheet) |
Typical Applications
EPC144LC20 is suitable for 6 applications: Altera FLEX 6000 Series FPGA Configuration, ACEX 1K FPGA Configuration Storage, MAX 7000 CPLD Configuration and Glue Logic, Legacy Industrial Controller Retrofitting, Telecom Line Card Design, Military and Aerospace Legacy Systems.
Altera FLEX 6000 Series FPGA Configuration
The EPC144LC20 stores the configuration bitstream for legacy Altera FLEX 6000 FPGAs such as the EPF6010A and EPF6016, providing 144 Kbit of non-volatile serial memory matched to the FPGA's compressed bitstream size. The PROM connects directly to the FPGA's DATA, DCLK, nCONFIG, nSTATUS, and CONF_DONE pins and clocks the bitstream into the FPGA on power-up via the EPC serial protocol. Designers should connect the EPC144LC20's nCS pin to ground (always selected) and use a 10 kohm pull-up on nCONFIG. Compared to an EPROM-based configuration solution, the single-chip EPC144LC20 reduces board area by approximately 70% and eliminates external oscillator circuitry.
Recommended
ACEX 1K FPGA Configuration Storage
For ACEX 1K FPGAs (EP1K10, EP1K30, EP1K50), the EPC144LC20 serves as a compact configuration memory storing the compressed bitstream. ACEX 1K devices typically require 60-120 Kbit of configuration data after compression, fitting comfortably within the EPC144LC20's 144 Kbit capacity. The device is in-system programmable via JTAG using Quartus II, eliminating the need for a separate pre-programming step at the board house. The 20-pin LCC package is well suited to industrial temperature range designs common in ACEX 1K factory-automation applications. Estimated: configuration time at 10 MHz DCLK for a 100-Kbit bitstream is approximately 10 ms.
Recommended
MAX 7000 CPLD Configuration and Glue Logic
Although MAX 7000 CPLDs do not require external configuration memory, the EPC144LC20 is often used in mixed MAX 7000 + FLEX designs to configure the FPGAs while the MAX devices provide glue logic and bus interfacing. The 20-pin LCC footprint is small enough to sit adjacent to a TQFP-100 MAX CPLD on the same PCB layer. This pairing was extremely common in 1990s and early-2000s telecom line-card designs. The EPC144LC20's JTAG chain can be shared between the MAX CPLD and the FLEX FPGA, allowing single-cable in-system programming of both devices using a USB-Blaster.
Recommended
Legacy Industrial Controller Retrofitting
When retrofitting legacy industrial controllers that originally used EPROM-based FPGA configuration, the EPC144LC20 provides a single-chip replacement that eliminates the parallel EPROM, address latch, and configuration clock oscillator. The 20-pin LCC package drops into the same board footprint as the original 28-pin EPROM with minor wiring changes (serial DATA replaces parallel data bus). The EPC144LC20 supports in-field JTAG reprogramming, enabling firmware updates without removing the controller from service. This is particularly valuable for legacy PLC, CNC, and SCADA systems where the original Altera FPGA is still functional but the configuration EPROM has failed.
Recommended
Telecom Line Card Design
In telecom line cards using Altera FLEX 10K or APEX 20K devices for packet processing and SERDES interfacing, the EPC144LC20 holds the FPGA bitstream in non-volatile storage with industrial temperature grade support. The 144-Kbit capacity is ideal for FLEX 10K10 and FLEX 10K20 designs common in T1/E1 line interface units, while larger FLEX 10K100 designs require the EPC2 instead. The EPC144LC20's low standby current (<100 uA estimated) minimizes power consumption in always-on telecom infrastructure. The LCC-20 package withstands the thermal cycling of outdoor telecom enclosures better than plastic QFP variants.
Recommended
Military and Aerospace Legacy Systems
The LCC-20 (Leadless Chip Carrier) package of the EPC144LC20 offers superior thermal cycling and vibration performance compared to leaded packages, making it well suited to military and aerospace legacy systems. The part supports the industrial temperature range (-40C to +85C) and is compatible with Altera's military-grade FLEX and ACEX variants. Programmers supporting the EPC144LC20 include the Data I/O Unifam, BP Microsystems, and CSM Micro II. When designing new systems for MIL-STD-810 environments, the EPC144LC20 is preferred over the PLCC-20 variant for its leadless construction.
Recommended
Recommended Products Summary
Engineering reference data for EPC144LC20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC1441LC20 | EPC144LC20-3 | EPC144ILC20 | EPC144ICC20 | EPC1441-LC20 |
|---|---|---|---|---|---|---|
| Package | LCC-20 | LCC-20 - same | LCC-20 - same | LCC-20 - same | LCC-20 - same | LCC-20 - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Memory Capacity | 144 Kbit | 144 Kbit | 144 Kbit | 144 Kbit | 144 Kbit | 144 Kbit |
| Supply Voltage | 3.0V to 5.5V | 3.0V to 5.5V | 3.0V to 5.5V | 3.0V to 5.5V | 3.0V to 5.5V | 3.0V to 5.5V |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) |
| Lifecycle Status | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Obsolete (estimated) | Last-time-buy |
| Param Match Percentage | 100% | 100% | 100% | 95% | 90% | 100% |
Key Differentiators
- Direct Altera/Intel second-source availability (vs EPC1441LC20)
- Industrial temperature grade variant available (vs EPC144ICC20)
- Compact LCC-20 leadless package (vs EPC144LC20 in PLCC-20)
Design Notes
Place one 0.1 uF ceramic decoupling capacitor as close as possible to each VCC pin (pins 1 and 19) and one bulk 10 uF tantalum or ceramic capacitor within 0.25 inch of the device. According to the Altera Configuration Devices datasheet, the EPC144LC20's internal configuration oscillator draws sharp current transients during bitstream clocking; insufficient decoupling can cause configuration failures manifesting as CRC errors. For multi-PROM configurations, place each EPC device on its own local decoupling network to prevent cross-coupling noise.
The serial configuration interface signals (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) are high-impedance CMOS outputs and should be routed as short, impedance-controlled traces (50 ohm characteristic impedance recommended for runs >2 inches). According to the Altera Configuration Handbook, keep configuration traces away from switching power supply and clock signals to avoid coupling noise that corrupts the bitstream. Add 10 kohm pull-up resistors on nCONFIG and nSTATUS per Altera reference design AN-116. Estimated: signal integrity margin with 50 ohm routing and 10 kohm pull-ups supports up to 8 inch trace lengths at 10 MHz DCLK.
Do not confuse the EPC144LC20 with the EPC2 or EPC8 - those are higher-capacity configuration PROMs (2 Mbit and 8 Mbit respectively) and are NOT drop-in compatible due to differing pin assignments on the LCC package. According to the Altera Configuration Devices datasheet, the EPC144LC20 is one-time programmable (OTP); verify the bitstream is correct before programming because the device cannot be erased. When using JTAG, ensure the chain order places the EPC144LC20's TDI/TDO between the FPGA's TDO and the JTAG connector's TDI to allow single-cable programming of both devices.
Compliance Information
RoHS and REACH compliance status not found in verified web data; marked [DATA_NEEDED] in specs. Lead-free confirmed by Altera packaging information. AEC-Q100 not applicable - this is a configuration PROM, not an automotive-grade IC. Industrial temp variants (EPC144ILC20) exist for harsh-environment applications.
