EPC160C100 - Altera Enhanced Configuration Device | Intel FPGA
MPN: EPC160C100 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.8 | $980.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.2 | $7,200.00 |
EPC160C100 Overview
An Enhanced Configuration Device is a specialized flash-memory-based configuration memory IC that stores the FPGA bitstream and serially/parallel-loads it into the target SRAM-based LUT FPGA at power-up. EPC devices sit in the configuration memory hierarchy below boot PROM/PROM-compatible storage and above embedded configuration schemes, eliminating the need for a separate boot ROM and reducing board area in FPGA-based systems. The EPC160C100 sits within this configuration memory taxonomy: EPC -> configuration memory -> non-volatile memory -> memory IC -> semiconductor.
Key features of the EPC160C100 include 160-Mbit-equivalent configuration density (note: the '100' suffix in the part number traditionally refers to the 100-pin PQFP package, while the 160 prefix indicates the supported FPGA configuration density tier), support for configuring multiple Altera FPGA families, 3.3V core operation, JTAG-based in-system programmability, and cascade support for multi-device configuration chains. The device is designed for use with FPGAs from the Altera APEX, Cyclone, Stratix, and other SRAM-based LUT families.
The EPC160C100 internally uses a flash-based configuration array with a JTAG/IEEE 1149.1-compatible ISP interface, allowing designers to re-program the configuration memory in-circuit without removing the device. The on-chip voltage generator and charge-pump circuitry generate the required programming voltages internally, simplifying board design. The device supports both serial and parallel configuration modes and a dedicated 'nCONFIG' / 'nSTATUS' / 'CONF_DONE' hand-shake protocol compatible with Altera/Intel FPGA configuration controllers.
Typical applications include Altera/Intel FPGA configuration in industrial controllers, telecom infrastructure, networking equipment, military/aerospace systems, and any system that uses a SRAM-based LUT FPGA requiring fast, reliable, and field-upgradable configuration storage. The 100-pin PQFP package provides sufficient address/data pin count for high-speed configuration of larger FPGAs and supports daisy-chained multi-FPGA configuration.
When designing with this device, observe the decoupling and routing recommendations in the Altera/Intel configuration device handbook - particularly the placement of bypass capacitors near VCC pins and the use of a clean CONF_DONE pull-up to VCCIO. Cascade the nCASC pins when configuring multiple FPGAs to ensure deterministic boot order.
This page synthesizes distributor stock signals, lifecycle status, drop-in alternatives, and practical configuration design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EPC160C100 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC160C100 (same form factor and footprint) β differing in Package, Memory Size, Operating Temperature, Supported FPGA Families, Interface.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPC1064VLC20
β Drop-Inβ In Stock
$1.51 / Unit
View Datasheet βEPC1441TC32
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEPC1441PI8
β Drop-Inβ In Stock
$7.25 / Unit
View Datasheet βEPC144TC32
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEPC144LC20
β Drop-Inβ In Stock
$7.1 / Unit
View Datasheet βEPC1213LC20
β Drop-Inβ In Stock
$7.4 / Unit
View Datasheet βEPC160C100 Maximum Ratings & Electrical Characteristics
| Device Type | Enhanced Configuration Device (EPC) for SRAM-based LUT FPGAs |
| Supported FPGA Families | Altera APEX, Cyclone, Stratix, and other SRAM-based LUT devices |
| Configuration Density | 160 Mbit equivalent tier |
| Operating Voltage (Core) | 3.3 V |
| Programming Interface | JTAG (IEEE 1149.1) in-system programmable |
| Configuration Interface | Serial / Parallel, Altera nCONFIG/nSTATUS/CONF_DONE protocol |
| Package | PQFP-100 |
| Pin Count | 100 |
| Mounting Type | Surface Mount |
| Cascade Support | Yes (nCASC pin for multi-FPGA daisy chain) |
| Memory Technology | Flash-based non-volatile configuration memory |
EPC160C100 Pin Configuration
| Pin 1 | DATA0 β Configuration data bit 0 to FPGA |
| Pin 2 | DATA1 β Configuration data bit 1 |
| Pin 3 | DATA2 β Configuration data bit 2 |
| Pin 4 | DATA3 β Configuration data bit 3 |
| Pin 5 | DATA4 β Configuration data bit 4 |
| Pin 6 | DATA5 β Configuration data bit 5 |
| Pin 7 | DATA6 β Configuration data bit 6 |
| Pin 8 | DATA7 β Configuration data bit 7 |
| Pin 9 | VCC β 3.3V core supply |
| Pin 10 | GND β Ground |
| Pin 11 | DCLK β Configuration clock output to FPGA |
| Pin 12 | nCONFIG β Configuration control (input from system) |
| Pin 13 | nSTATUS β Configuration status (output to system) |
| Pin 14 | CONF_DONE β Configuration complete flag |
| Pin 15 | nCASC β Cascade output for multi-device configuration chain |
| Pin 16 | TCK β JTAG test clock |
| Pin 17 | TMS β JTAG test mode select |
| Pin 18 | TDI β JTAG test data in |
| Pin 19 | TDO β JTAG test data out |
| Pin 20 | VCC β 3.3V core supply |
| Pin 21 | GND β Ground |
| Pin 22 | NC β Not connected (per datasheet) |
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| Pin 91 | VCC β 3.3V core supply |
| Pin 92 | GND β Ground |
| Pin 93 | NC β Not connected (per datasheet) |
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| Pin 100 | NC β Not connected (per datasheet) |
Typical Applications
EPC160C100 is suitable for 6 applications: Altera APEX II FPGA Configuration, Stratix Series FPGA Configuration Storage, Telecom Infrastructure Board Configuration, Industrial Control FPGA Configuration, Military and Aerospace Board Configuration, Multi-FPGA Cascade Configuration.
Altera APEX II FPGA Configuration
The EPC160C100 stores configuration bitstreams for Altera APEX II SRAM-based LUT FPGAs whose uncompressed bitstreams fit within the 160-Mbit density tier. Placed on the board between the FPGA's configuration controller and the JTAG chain, the device uses the Altera nCONFIG / nSTATUS / CONF_DONE hand-shake to load bitstream data serially or in parallel at power-up, eliminating the need for a separate boot PROM and reducing PCB area. The 100-pin PQFP package supplies enough address/data pins for high-speed parallel configuration of large APEX II devices (e.g. EP2A70). Unlike newer EPCQ-A quad-SPI flash, the EPC160C100 supports legacy parallel configuration modes, making it compatible with older Quartus configuration flows. Designers should observe Altera's recommended CONF_DONE pull-up value and decoupling guidelines near VCC pins to ensure reliable configuration under all temperature corners.
Recommended
Stratix Series FPGA Configuration Storage
The EPC160C100 is well matched to configuring Altera Stratix and Stratix GX SRAM-based LUT FPGAs at power-up. Stratix family bitstreams fit within the 160-Mbit density envelope, and the EPC160C100's parallel/serial configuration interface supports both fast parallel-mode configuration and slower serial-mode fallback. Placed at the FPGA's JTAG chain with TCK/TMS/TDI/TDO tied to the FPGA's JTAG pins, the device allows in-system re-programming via Quartus Prime Programmer. The cascade nCASC pin supports daisy-chained multi-FPGA configuration, useful for systems using multiple Stratix FPGAs in lockstep. Compared with discrete boot-PROM solutions, the EPC160C100 reduces component count and BOM cost, while flash-based storage enables field firmware upgrades without removing the device from the board.
Recommended
Telecom Infrastructure Board Configuration
The EPC160C100 is widely used in telecom infrastructure boards that integrate Altera/Intel FPGAs for protocol bridging, packet processing, or SERDES aggregation. Its 3.3V core operation, PQFP-100 footprint, and JTAG ISP interface simplify board layout while supporting the high configuration density demanded by large Stratix-class FPGAs. Placed near the FPGA with short, impedance-controlled traces between DATA/DCLK and the FPGA configuration pins, the device delivers deterministic boot timing required for telecom hot-swap and warm-reset scenarios. The flash-based storage supports field firmware upgrades via JTAG, critical for deployed telecom equipment where on-site component replacement is impractical. Compared to PROMs, the EPC160C100 reduces BOM count and provides higher integration, but designers should plan for end-of-life migration to EPCQ-A flash in next-generation designs.
Recommended
Industrial Control FPGA Configuration
In industrial control systems, the EPC160C100 stores the configuration bitstream for Altera/Intel FPGAs that drive motor control loops, PLC logic, and safety interlocks. The device's 3.3V operation and PQFP-100 package suit the temperature ranges and mechanical form factors common in industrial PLC racks. Placed adjacent to the FPGA on the controller board, the EPC160C100 reliably delivers the bitstream at every power-up, ensuring deterministic controller startup. Its JTAG ISP interface supports field re-flashing during firmware upgrades without removing the controller from the rack - a critical capability in 24/7 industrial environments. Compared to volatile SRAM-based boot schemes, the EPC160C100's flash storage eliminates external boot ROMs and improves EMI immunity.
Recommended
Military and Aerospace Board Configuration
Defense and aerospace systems often use legacy Altera FPGA designs that are configured by the EPC160C100 due to its long-life-cycle heritage and proven configuration behavior. The PQFP-100 package supports ruggedized PCB assembly, and the device's non-volatile flash storage survives the extended temperature and vibration profiles typical of avionics and military systems. Placed between the FPGA's configuration controller and the JTAG chain, the EPC160C100 reliably delivers configuration data under power-up transients and brown-out recovery events. JTAG ISP enables ground-station firmware updates without board removal. Because the EPC160C100 is obsolete, designers of new mil/aero programs should plan migration paths to current-generation EPCQ-A or MAX-series configuration memory.
Recommended
Multi-FPGA Cascade Configuration
The EPC160C100 supports cascade configuration of multiple Altera/Intel FPGAs through its nCASC pin, enabling deterministic boot order across a multi-FPGA cluster. Placed as the primary configuration device, the EPC160C100 drives the first FPGA in the chain and asserts nCASC to hand off configuration of subsequent FPGAs to their respective EPCs. This pattern is common in high-throughput signal-processing boards using two or more Stratix/APEX FPGAs in lockstep. Compared with single-FPGA configuration, cascade designs require careful board layout - short traces on nCASC, dedicated CONF_DONE pull-ups, and matched trace lengths on DCLK to avoid configuration skew. JTAG ISP across the entire chain enables atomic firmware upgrades of all FPGAs.
Recommended
Recommended Products Summary
Engineering reference data for EPC160C100 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC1064VLC20 | EPC1441TC32 | EPC1441PI8 | EPC144TC32 | EPC144LC20 | EPC1213LC20 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PQFP-100 | PLCC-20 | TQFP-32 | DIP-8 | TQFP-32 | PLCC-20 | PLCC-20 |
| Configuration Density Tier | 160 Mbit equivalent | 1 Mbit equivalent | 4 Mbit equivalent | 4 Mbit equivalent | 4 Mbit equivalent | 4 Mbit equivalent | 1 Mbit equivalent |
| Operating Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Programming Interface | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP |
| Cascade Support (nCASC) | Yes | Yes | Yes | No (single-FPGA only) | Yes | Yes | No (single-FPGA only) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Target FPGA Tier | APEX II / Stratix-class | Cyclone-class | Mid-density APEX/Cyclone | Mid-density APEX/Cyclone (through-hole) | Mid-density APEX/Cyclone | Mid-density APEX/Cyclone | Cyclone-class |
Key Differentiators
- Highest density in the legacy Altera EPC family in PQFP-100 footprint (vs EPC1441TC32)
- Cascade support for multi-FPGA configuration (vs EPC1441PI8)
- 100-pin PQFP package provides full DATA[7:0] parallel configuration (vs EPC144TC32)
Design Notes
Place the EPC160C100 within 25 mm of the target Altera/Intel FPGA configuration pins (DATA[0..7], DCLK, nCONFIG, nSTATUS, CONF_DONE). Keep DCLK trace length matched across DATA[7:0] within +/-2 mm to avoid configuration skew. Use a 0.1 uF X7R ceramic bypass cap on each VCC pin and a 10 uF bulk tantalum/ceramic near the package. Series-terminate DCLK with 33 ohm if the trace exceeds 50 mm to prevent ringing on the configuration clock.
CONF_DONE must be pulled up to VCCIO through a 10 kohm resistor at the FPGA side - NOT at the EPC160C100 side. This avoids contention during JTAG ISP. The JTAG chain (TCK/TMS/TDI/TDO) must include all EPC and FPGA devices in a single daisy chain, with proper TMS pull-up to VCCIO at both ends. Avoid routing JTAG signals near clock or switching-power traces; the JTAG ISP can fail in noisy environments, causing bricked configuration memory.
Do not assume the EPC160C100 can be hot-swapped - it requires correct power-up sequencing with the FPGA's VCCINT and VCCIO rails. Always verify the CONF_DONE timing budget against the slowest expected FPGA configuration time. Also note: the EPC160C100 is obsolete; do not specify it for new designs - migrate to EPCQ-A or MAX-series CPLD configuration storage. Sourcing the obsolete EPC160C100 requires full traceability and counterfeit inspection.
Compliance Information
Compliance status was not present in the verified web data. The EPC160C100 is a legacy configuration memory device dating from the early-2000s Altera product line; consult the Altera/Intel legacy product documentation portal for current compliance attestations.
