EPC1L20 vs EPC1LC120 Comparison
Detailed side-by-side comparison of EPC1L20 by Altera and EPC1LC120 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPC1LC120
EPC1LC120 - 1Mb SRAM Config Memory, 8MHz, 120-Pin LQFP | Altera
EPC1LC120 β ActiveSpecification Comparison
| Parameter | EPC1L20 | EPC1LC120 |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3.75 | $9.30 |
| Memory Type | OTP Configuration PROM (Flash) | Serial Configuration Memory (Flash-based, non-volatile) |
| Memory Size | 1 Mbit | β |
| Configuration Clock (max) | 8 MHz | β |
| Flash Access Time | 90 ns (approx.) | β |
| Max Read Bandwidth | 160 Mbps (16-bit DQ bus) | β |
| Interface | Serial / FPP configuration + JTAG (IEEE 1149.1) | Altera / Intel proprietary FPGA-configuration serial bus (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Supply Voltage | 3.3 V (typical) | [DATA_NEEDED: VCC range] |
| Programmability | One-Time Programmable (OTP) | β |
| Package | 20-pin PLCC (9x9 mm) | LQFP-120 (Low-profile Quad Flat Pack) |
| Mounting Type | Through-Hole / Socket | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | β |
| JTAG / ISP Support | Yes (IEEE 1149.1) | β |
| Compatible FPGA Series | Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Memory Density | β | 1 Mbit |
| Serial Clock Frequency (DCLK) | β | 8 MHz |
| Supported FPGA Families | β | APEX 20K, ACEX 1K, Cyclone, MAX, Mercury, Stratix-class |
| Operating Temperature Range | β | [DATA_NEEDED: operating temperature range] |
| Programming | β | Factory / JTAG via Altera programming tools |
| MSL Level | β | [DATA_NEEDED: MSL rating] |
| Configuration Mode | β | Serial configuration of SRAM-based FPGAs |
| Compatible Bitstream Width | β | Serial |